below is my code for reference. basially i am setting a variable from my test build phase and trying to get it inside my top module. i have tried multiple syntax but not able to get it. is there a limitation to get a variable inside a top level module ?
class my_test extends uvm_test
`uvm_component_utils(my_test)
my_regmodel regmodel;
//skipping loads of code here just showing build phase
function void smmu_base_test::build_phase(uvm_phase phase);
my_regmodel regmodel;
initial begin #10ns;//dealy to make sure its set before get
if (!uvm_config_db #(my_regmodel)::get(uvm_root::get(),“uvm_test_top”,“regmodel”, regmodel)) uvm_fatal ("top", "pawan Did not get a register model from test smmu top") else uvm_info(“top” ,“successfully got regmodel smmu top”,UVM_LOW);
end
With run_test you are starting the creation of your dynamic part of your tesbench.
Using a simple delay does not solve your problem. Use instead a uvm_event, triggered after the connect_phase in your dynamic testbenc part. In the toplevel module you can start your get to the config_db after seeing this event.
In reply to pawan:
With run_test you are starting the creation of your dynamic part of your tesbench.
Using a simple delay does not solve your problem. Use instead a uvm_event, triggered after the connect_phase in your dynamic testbenc part. In the toplevel module you can start your get to the config_db after seeing this event.
In reply to pawan:
With run_test you are starting the creation of your dynamic part of your tesbench.
Using a simple delay does not solve your problem. Use instead a uvm_event, triggered after the connect_phase in your dynamic testbenc part. In the toplevel module you can start your get to the config_db after seeing this event.
i have tried using events and it still fails with same error saying regmodel not found. now i wait for event rather than delay and trigger event when build phase is complete.