Use of Interface in Sequence

Hi,
Can we get interface in sequence library using config_db get()?If yes,then where to write?
I am writing config_db get() in my seq_lib body() task but it shouts error.

Thanks,

In reply to Salman94:

You should never reference an interface in a sequence. An interface should only be used in a driver or a monitor.

If you provide more information about what you are trying to accomplish, an alternate solution can be provided.

Kerul,
I implemented what you suggested but it shouts error.
Below is snippet of my code and error.
Code:
class wr_seq extends …;
`uvm_declare_p_sequencer(axi_master_sequencer)

task body();
@(posedge p_sequencer.vif.ck_t);

endtask
endclass

Error:
Error-[MFNF] Member not found
Could not find member ‘vif’ in class ‘axi_master_sequencer’

In reply to Salman94:

show me axi_master_sequencer code snippet where you have taken handle of vif

In reply to Salman94:

It is not recommended to use pin-level signals in a sequence, because you are loosing the benfits of TLM or in other words: using pin-level signals there means you do not really understand TLM.