Use of defparam statement inside $test$plusargs condition in tb_top module in UVM

UVM
,
1

Hi,
I am trying to override the parameter value from 1000 to 0000 inside one RTL file from our tb_top module in UVM based testbench only for one single testcase named as “Clock_observation_test”.

So, I am using defparam statement in tb_top and running this test only but I am getting below error:

  1. Used 1st approach:
    module tb_top;
    initial
    begin
    if($test$plusargs(“clock_observation_test”)) begin
    defparam dut_wrapper.dut.u_ddr54phy_16b_v1p0_dft_gasket.uros_cntl_inst.mrk_mcp_rosen.CdcDestSetup = 0000;
    end
    end
    endmodule

Syntax Error getting:
Error-[SE] Syntax error
Following verilog source has syntax error :
“/proj/ct_dftgasket_verif_rv_sn/users/kapkhare/viola_new/out/linux_3.10.0_64.VCS/viola/library/ddr54phy_16b_v1p0_dft_gasket-
viola/pub/src/verif/tb/top_sg4_tb.sv”,
243: token is ‘defparam’
defparam dut_wrapper.dut.u_ddr54phy_16b_v1p0_dft_gasket.uros_cntl_inst.mrk_mcp_rosen.CdcDestSetup = 00000;

  1. Use 2nd approach (without using initial block):

    module tb_top;
    if($test$plusargs(“clock_observation_test”)) begin
    defparam dut_wrapper.dut.u_ddr54phy_16b_v1p0_dft_gasket.uros_cntl_inst.mrk_mcp_rosen.CdcDestSetup = 0000;
    end
    endmodule

Syntax Error getting:
Error-[V2KGEUV] Unknown or bad value for genvar
/proj/ct_dftgasket_verif_rv_sn/users/kapkhare/viola_new/out/linux_3.10.0_64.VCS/viola/library/ddr54phy_16b_v1p0_dft_gasketviola/pub/src/verif/tb/top_sg4_tb.sv, 242
" if ($test$plusargs(“include_clock_observation_test”)) begin : genblk1
defparam dut_wrapper.dut.u_ddr54phy_16b_v1p0_dft_gasket.uros_cntl_inst.mrk_mcp_rosen.CdcDestSetup = 0; end"
Instance/Generate block name: tb
Elaboration time unknown or bad value encountered for generate if-statement
condition expression.
Please make sure it is elaboration time constant.

Can any give me the correct piece of code means how can I deal with this kind of situation in tb_top?

Thanks
Kapil

2

In reply to kapil khare:

A defparam is an elaboration construct; it does not execute at run-time and cannot be placed in a procedural block of code. That is why 1st approach does not work.

a generate-if is is an elaboration construct; you cannot not use non-constant expressions like $test$plusargs which gets evaluated at run-time. That is why 2nd approach does not work.

Without knowing how CdcDestSetup is being used, it is difficult to suggest a workaround. Some tool provide mechanisms for overriding parameters from the command line at run-time. You would have to consult your tool’s user manual or contact your tool vendor directly for support.

3

In reply to dave_59:

How to change the value/pass value to the parameterized module based on randomization?
For example
rand bit xyz;

Module instantiation with default value.
eg #(.PARAM_A (0)) eg1 (…); // But PARAM_A should be assigned based on the random variable xyz

4

In reply to mprasad11:
Variables, random or not, cannot be used to define/override parameter values.

https://verificationacademy.com/forums/ovm/randomizing-module-parameters