A quick clarification in uvm ports, ie:
Till now in most of my test benches I always use tlm analysis ports. But I am wondering whats the difference between the following ports.
Whats the use case for each of them.
b) Lets assume I want to connect two components across the hierarchy. also lets say the source is subcompA and target is subcompB, and subcompA is instanced in compA and subcompB is instanced in compB. So how should I connect the ports here, is it option 1) or 2) or something else.
1) Port(in subcompA) -> port (in compA) -> export (in compB) -> impl Port (in subcompB)
2) Port(in subcompA) -> export (in compA) -> export (in compB) -> impl Port (in subcompB)
Thanks for the help