I have been trying to develop USB 2.0 Host verification Architecture . Right now I have implemented USB 2.0 Peripheral BFM and Phy Models for interaction with DUT. Now I need to develop scoreboard for the same.Host has a AHB Interface for DUT configuration.Currently I’m using various AHB Sequences to generated traffic and various functions.
For predictor side I have two ways in my mind
1- Create complete software model for USB 2.0 Host for bit level simulation and compare with produced output. If I do the then I will be able to use same AHB Sequences that I provide to Host DUT.
2- Create a Higher level sequence (transaction level) for Host DUT . Create another layer that will decode this Higher level and convert into desired AHB sequence for particular action . In this fashion I will be able to use Transaction level DUT sequences to compare with Transaction level out put of Monitor .
Can someone put light on the Industry uses of these methods . Which one is preferable.