Dear All,
I came across usage of vitial interface and interface, But I’m confused it.
For example,
-agent.sv
class sys_agent extends uvm_agent;
....
virtual interface sys_if_vif;
...
virtual function void build_phase(uvm...)
...
dirver.vif = vif;
monitor.vif = vif;
endfunction
endclass
-driver.sv
class sys_monitor extends uvm_monitor;
...
virtual sys_if vif; <--Is this correct usage?
...
endclass
from 2 files, we can see the usage of virtual interface declared.
But I’m confused that why “vitual interface sys_if vif” instead vitual sys_if vif in driver.sv?
dave_59
December 10, 2021, 5:48am
2
In reply to UVM_LOVE :
This is not legal syntax.
virtual interface sys_if_vif;
In reply to dave_59 :
Sorry my typo,
What is the difference usage between
type1.
virtual interface sys_if_vif vif;
and
type2.
virtual sys_if_vif vif;
I came across some examples such as type1 or type2.
I’m confused it. So I checked it from
Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.
But they are working as the same.
dave_59
December 10, 2021, 4:29pm
4
In reply to UVM_LOVE :
The syntax for declaring a virtual interface variable is
virtual [ interface ] interface_identifier [ parameter_value_assignment ] [ . modport_identifier ]
That means the presence of the
interface interface keyword is optional. Don’t ask me why Verilog/SystemVerilog has so many ways to do the same thing.
tfitz
December 10, 2021, 10:46pm
5
In reply to dave_59 :
Don’t ask me why Verilog/SystemVerilog has so many ways to do the same thing.
Trust me, if Dave doesn’t know why something is the way it is in Verilog/SystemVerilog, it is unknowable.