Hello all,
I am seeing below error message in my log
UVM_INFO @ 34000: reporter [RegModel] Read register via map regmodel.uvm_reg_map: regmodel.XXX_APRB_CTL=0
UVM_ERROR /tools/synopsys/2011.12-SP1/etc/uvm/src/reg/uvm_reg.svh(2906) @ 34000: reporter [RegModel] Register “regmodel.XXX_APRB_CTL” value read from DUT (0x0000) does not match mirrored value (0x03f9)
But i am seeing reset value on the bus correctly, which i captured through monitor
UVM_INFO …/env/xxx_master_monitor.sv(64) @ 34000: uvm_test_top.xxx_config_tb0.xxx0.master[0].monitor [XXX_MASTER_MONITOR] -------------------------------------------------
Name Type Size Value
item xxx_master_transaction - @822
rd rw_e 32 READ
status status_e 32 IS_OK
data integral 16 'h19
addr integral 8 'h1
But when i print bus2reg item i am not seeing the value .
UVM_INFO …/env/ral_single.sv(65) @ 34000: reporter [reg2tr] bus2reg information…
Name Type Size Value
tr xxx_master_transaction - @817
rd rw_e 32 READ
status status_e 32 IS_OK
data integral 16 'h0
addr integral 8 'h1
begin_time time 64 30000
end_time time 64 34000
depth int 32 'd2
parent sequence (name) string 20 uvm_reg_hw_reset_seq
parent sequence (full name) string 20 uvm_reg_hw_reset_seq
sequencer string 52 uvm_test_top.xxx_config_tb0.xxx0.master[0].sequencer
These are the steps i followed.
- Generated REGMODEL from ralgen
- Integrated into my environment
- created adapter class and register sequence extending from uvm_reg_sequence
- connected default bus sequencer to regmodel
In my testcase i am starting hardware reset sequence like below:
uvm_reg_hw_reset_seq reg_reset_seq;
reg_reset_seq.model = xxx_config_tb0.xxx0.regmodel;
reg_reset_seq.start(null); // assuming the default sequencer has been set up for the frontdoor
Can anyone let me know i am i missing any connection to adapter?
I am using auto prediction
Thanks
Raghavendra