Usage of build-in hardware reset register sequence

Hello all,

I am seeing below error message in my log

UVM_INFO @ 34000: reporter [RegModel] Read register via map regmodel.uvm_reg_map: regmodel.XXX_APRB_CTL=0
UVM_ERROR /tools/synopsys/2011.12-SP1/etc/uvm/src/reg/uvm_reg.svh(2906) @ 34000: reporter [RegModel] Register “regmodel.XXX_APRB_CTL” value read from DUT (0x0000) does not match mirrored value (0x03f9)

But i am seeing reset value on the bus correctly, which i captured through monitor

UVM_INFO …/env/xxx_master_monitor.sv(64) @ 34000: uvm_test_top.xxx_config_tb0.xxx0.master[0].monitor [XXX_MASTER_MONITOR] -------------------------------------------------
Name Type Size Value

item xxx_master_transaction - @822
rd rw_e 32 READ
status status_e 32 IS_OK
data integral 16 'h19
addr integral 8 'h1

But when i print bus2reg item i am not seeing the value .

UVM_INFO …/env/ral_single.sv(65) @ 34000: reporter [reg2tr] bus2reg information…

Name Type Size Value

tr xxx_master_transaction - @817
rd rw_e 32 READ
status status_e 32 IS_OK
data integral 16 'h0
addr integral 8 'h1
begin_time time 64 30000
end_time time 64 34000
depth int 32 'd2
parent sequence (name) string 20 uvm_reg_hw_reset_seq
parent sequence (full name) string 20 uvm_reg_hw_reset_seq
sequencer string 52 uvm_test_top.xxx_config_tb0.xxx0.master[0].sequencer

These are the steps i followed.

  1. Generated REGMODEL from ralgen
  2. Integrated into my environment
  3. created adapter class and register sequence extending from uvm_reg_sequence
  4. connected default bus sequencer to regmodel

In my testcase i am starting hardware reset sequence like below:
uvm_reg_hw_reset_seq reg_reset_seq;

reg_reset_seq.model = xxx_config_tb0.xxx0.regmodel;
reg_reset_seq.start(null); // assuming the default sequencer has been set up for the frontdoor

Can anyone let me know i am i missing any connection to adapter?

I am using auto prediction

Thanks
Raghavendra

Is this the only register that fails the test? - Check the register model
Is the adapter implemented correctly? - Check the direction of the transfer on the bus2reg method for instance.

If you write a sequence that does a read from this register, what value do you read back?

In reply to mperyer:

In my register model, i kept only one register to find out the problem.

I have shown the adapter in my post, whatever is implemented.

In reset sequence, i am trying to read the reset value of the mentioned register, but i am getting 0x0000 from DUT

Except you don’t show the source code for the adapter.

It also occurs to me that your driver may not be returning the read data correctly. This is a separate path from the monitor.

How do you return the response from the driver?

In reply to mperyer:

Here, i am using auto prediction.

How do you return the response from the driver?

In my driver, read data from bus into the transaction field.

snippet::

where trans is the transaction handle extended from uvm_sequence_item
vif is the virtual interface

if(trans.rd) begin
vif.xxx_first_addr = trans.addr;
trans.data = vif.xxx_first_read_data;
end

In adapter from bus2reg, it will drive to uvm_reg_bus_op

virtual function void bus2reg (uvm_sequence_item bus_item, ref uvm_reg_bus_op rw);
xxx_master_transaction tr;

if (!$cast(tr, bus_item)) begin
`uvm_fatal(“NOT_xxX_TYPE”,“Provided bus_item is not of the correct type”)
return;
end

rw.kind = tr.rd ? UVM_READ:UVM_WRITE ;
rw.addr = tr.addr;
rw.data = tr.data;
rw.status = UVM_IS_OK;

`uvm_info(get_type_name(),$sformatf(“bus2reg information…\n%s”, tr.sprint()), UVM_LOW)
endfunction

please let me know i am i missing any connection ?

Thanks
Raghavendra

It looks to me like your driver might not be returning the data correctly.

At least in the code snippet you shared, there would not be enough time from presenting the address on the virtual interface for the DUT to return data on the virtual interface to be assigned to the data field in your transaction.

In reply to mperyer:

In my driver, i am seeing read data driven from virtual interface to the transaction field correctly.

May be i am missing something here.

Can you please let me know how the read path flow has to be i.e from driver to model? if possible any example code?

Thank you for your support.

I resolved this problem.

response is not proper from driver to sequencer, that’s y i am not able to see read data path .

–Raghavendra

In reply to Raghavendra Reddy:

Hi,

How do I delay the time from presenting the address on the virtual interface for the DUT to return the correct data on the virtual interface to be assigned to the data field in the transaction.

Please explain the procedure ?