Hello,
Currently I am trying to bind few signals of VHDL entity to SV interface signals.
Syntax I’m using :
bind DUT:dut_inst ahb_if ahb_if_o(.<ahb_if signal> (entity signal))
I am going to send ahb_if_o as virtual interface to UVM config db and using UVC , drive stimulus to VHDL entity.
I want to know whether syntax I am using is correct and can we drive VHDL entity signal from UVC using virtual if like above?
In reply to Chandrashekhar Goudar:
Do you really need instance bind or entity/module is good enough? Instance binding can become tool specific syntax while module/entity binding can be vendor neutral. In anycase you should show any error you found with your simulator (As Dave asked).
Good Luck
Srini
www.verifnews.org
In reply to dave_59:
When I tried to bind instance, its not able to find that instance. I tried binding entity itself like below:
bind ENTITY_NAME ahb_if ahb_if_o( .ENTITY SIGNAL (AHB_IF SIGNAL));
for which I got following error,
Error-[SVA-COBMMI] Can only bind to modules or instances.
Can only bind to modules or module instances.
In reply to Chandrashekhar Goudar:
To me it looks like you are using VCS-MX from Synopsys in this case. If yes, use the flag -sva_bind_enable to get this going (for SVA binding to VHDL). Since this is Mentor forum, I will post a detailed example on a neutral forum/site @ http://www.veriflabs.com shortly. Meanwhile if you need urgent help on this specific option/usage, drop me an email via srini <> cvcblr
Regards
Srini
http://www.verifworks.com
In reply to Srini @ CVCblr.com:
Hi,
I am using VCS-MX only. I tried to another way where I created a wrapper module where I instantiate AHB interface and send it to SV-class tb.
And I am binding wrapper module outputs to vhdl entity inputs, for which I got another elab error which is currently being seen by VCS support. Error is,
Updating port RTL:<i/p signal> of mode IN is not allowed.
Please verify the port mapping for correctness.