Unwanted re-programming on same address of memory

UVM
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1

Hi,

I have Verilog model of Flash Memory and I am using UVM testbench for Verification.So Write,read,erase,etc… commands are fired on Flash Memory.
In my constraint random packet class cmd,addresses,and data inputs are there.(cmd,add[5],din)

My query is,…
Once write command is fired on one address, I don’t want to re-programming(re-Write) on same address location until erase operation is fired on this address location.

So How to set constraint in packet class for this scenario?

2

You create a list of address and use the inside operator to write a constraint that says when there is a write command, the address cannot be inside the list.

typedef bit [4:0] addr_t;
typedef enum {write, read, erase} cmd_e;
rand cmd_e cmd;
rand addr_t addr;
addr_t list[addr_t];

constraint no_erase { (cmd == write) -> !(addr inside {list});}
  function void post_randomize();
    case(cmd)
    write: list[addr] = addr; // add address to list
    erase: list.delete(addr);
    endcase
endfunction
3

In reply to dave_59:

Hi,Dave

Thanks For Quick Reply.

In My Code Addresses are “bit [7:0] add[5]”…so its array of addresses.
So, Can You please tell how to deal with these addresses?

4

In reply to kansagaratushar:

constraint no_erase { (cmd == write) -> foreach (add[i]) !(add[i] inside {list});}
  function void post_randomize();
    case(cmd)
    write: foreach (add[i]) list[add[i]] = add[i]; // add address to list
    erase: foreach (add[i]) list.delete(add[i]);
    endcase
endfunction
5

In reply to dave_59:

Thank You…