Unable to pass interface signal by reference to a task

I am trying to pass an interface signal by reference as shown in the below code. But, I see that the simulation hangs at @posedge statement. Even though I have used ref in the compare_freq task, it seems that the clkout value is always 0 and the simulation is stuck inside the task.

When I try to move the contents of the task inside run task, it works fine.

interface test_probe_intf();
  logic c1_pll_clk_out;
  logic cpu_pll_clk_out;
endinterface

class pll_cfg_test extends uvm_test;

  `uvm_component_utils(pll_cfg_test)

  virtual test_probe_intf test_probe_if;

  function new(string name = "pll_cfg_test", uvm_component parent = null);
    super.new(name, parent);
  endfunction : new

  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if(!uvm_config_db #(virtual test_probe_intf)::get(null, this.get_full_name(),"test_probe_if", test_probe_if)) begin
    `uvm_fatal(get_name(), "Unable to get test_probe_if handle");
    end
  endfunction : build_phase

  task run_phase (uvm_phase phase) ; 
    phase.raise_objection(this);

    ...

    fork
      compare_freq(test_probe_if.cpu_pll_clk_out,1000);
    join_none

    #20us;

	phase.drop_objection(this);
  endtask

  task compare_freq (ref logic clk_out, input real expected_freq);
    real clk_out_position;
    real clk_out_next_position;
    real clk_freq;
    
    @(posedge clk_out);
    //$realtime in nano seconds
    clk_out_position = $realtime;
    repeat(NUMBER_OF_CYCLES_TO_COUNT)
    @(posedge clk_out);
    clk_out_next_position = $realtime;
    
	...
	
  endtask:compare_freq

endclass : pll_cfg_test

In reply to umeshr1:

Works for me. Just a few extra lines would have made a complete runnable example

interface test_probe_intf();
   logic c1_pll_clk_out;
   logic cpu_pll_clk_out = 0;
   always #2 cpu_pll_clk_out++;
endinterface
import uvm_pkg::*;
`include "uvm_macros.svh"
 
class pll_cfg_test extends uvm_test;
 
  `uvm_component_utils(pll_cfg_test)
 
  virtual test_probe_intf test_probe_if;
 
  function new(string name = "pll_cfg_test", uvm_component parent = null);
    super.new(name, parent);
  endfunction : new
 
  function void build_phase(uvm_phase phase);
    super.build_phase(phase);
    if(!uvm_config_db #(virtual test_probe_intf)::get(null, this.get_full_name(),"test_probe_if", test_probe_if)) begin
    `uvm_fatal(get_name(), "Unable to get test_probe_if handle");
    end
  endfunction : build_phase
 
  task run_phase (uvm_phase phase) ; 
    phase.raise_objection(this);
    fork
      compare_freq(test_probe_if.cpu_pll_clk_out,1000);
    join_none
    #20us;
	phase.drop_objection(this);
  endtask
  task compare_freq (ref logic clk_out, input real expected_freq);
    real clk_out_position;
    real clk_out_next_position;
    real clk_freq;
 
    @(posedge clk_out);
    //$realtime in nano seconds
    clk_out_position = $realtime;
    repeat(10)
    @(posedge clk_out);
    clk_out_next_position = $realtime;
     $display("done"); 
  endtask:compare_freq
endclass : pll_cfg_test

module top;
   test_probe_intf intf();
   initial begin
      uvm_config_db #(virtual test_probe_intf)::set(null, "*","test_probe_if", intf);
      run_test("pll_cfg_test");
   end
endmodule

In reply to dave_59:

I could not see the “done” message being displayed, the test just completes without this. I guess it is a simulator issue then. I will contact the tool owner.