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  • Unable to compile a register model using registers of size 2048 bits

Unable to compile a register model using registers of size 2048 bits

UVM 6654
UVM Questa 2 questasim 5 #uvm 278 uvm register model 18
Marc43
Marc43
Full Access
32 posts
September 05, 2019 at 2:28 am

Hello,

I am unable to compile my register model using registers of size 2048 bits. I know that the default size is 64 and we have to do +define+UVM_REG_DATA_WIDTH=2048 when compiling UVM. But it doesn't work.

It complains with the same error as before:

UVM_FATAL verilog_src/uvm-1.1d/src/reg/uvm_reg_block.svh(1093) @ 0: reporter [RegModel] Register model requires that UVM_REG_DATA_WIDTH be defined as 2048 or greater. Currently defined as 64

I am using QuestaSim. Maybe I am not compiling the UVM that I should compile, did you have this error? How did you solve it?

Thanks,
Marc

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chr_sue
chr_sue
Full Access
3846 posts
September 05, 2019 at 4:06 am

In reply to Marc43:

UVM_REG_DATA_WIDTH is a parameter used by the RAL. With +define+ you are specifying a macro but not a parameter. Best is to set UVM_REG_DATA_WIDTH in your RAL package to the correct value.

Marc43
Marc43
Full Access
32 posts
September 05, 2019 at 5:36 am

In reply to chr_sue:

Quote:
In reply to Marc43:

UVM_REG_DATA_WIDTH is a parameter used by the RAL. With +define+ you are specifying a macro but not a parameter. Best is to set UVM_REG_DATA_WIDTH in your RAL package to the correct value.

Thank you for your reply. Then doing 

`define UVM_REG_DATA_WIDTH 2048
at the top of my RAL package, should work?

It does not work for me.

chr_sue
chr_sue
Full Access
3846 posts
September 05, 2019 at 6:37 am

In reply to Marc43:

No, this is again a macro.
In your RAL package do in a propriete place:
UVM_REG_DATA_WIDTH = 2048;

Vinay Jain
Vinay Jain
Full Access
83 posts
September 05, 2019 at 7:21 am

In reply to chr_sue:
I am not sure if that's true. as far as I remember it was macro. 

/uvm-1.2/src/reg/uvm_reg_model.svh:typedef  bit unsigned [`UVM_REG_DATA_WIDTH-1:0]  uvm_reg_data_t
uvm-1.1d/src/reg/uvm_reg_model.svh:typedef  bit unsigned [`UVM_REG_DATA_WIDTH-1:0]  uvm_reg_data_t ;

@Marc43 - you need to compile UVM source code with that define not your TB if that makes sense.

chr_sue
chr_sue
Full Access
3846 posts
September 05, 2019 at 7:37 am

In reply to Vinay Jain:

You are right. It is amacro. Then you have to compile the RAL with respect to this macro using the define.

Marc43
Marc43
Full Access
32 posts
September 05, 2019 at 7:46 am

In reply to chr_sue:

Yes, it's a macro. But how can you compile UVM with QuestaSim? I couldn't, and I've tried a LOT of times. Any tutorial?

dave_59
dave_59
Forum Moderator
10644 posts
September 05, 2019 at 8:20 am

In reply to Marc43:

This forum is not for tool specific issues. Please consult your tools User Manual for instructions on compiling your simulation for UVM.

— Dave Rich, Verification Architect, Siemens EDA

AL_verif
AL_verif
Full Access
16 posts
November 10, 2020 at 8:55 pm

In reply to chr_sue:

Quote:
In reply to Marc43:

No, this is again a macro.
In your RAL package do in a propriete place:
UVM_REG_DATA_WIDTH = 2048;

Where can I add it ?
could you please explain what do you mean "a propriate place" ?

I try to add it in my RAL package:
this way:
`UVM_REG_DATA_WIDTH = 550;
compilation failed.

I try to add in my package this way:
`define UVM_REG_DATA_WIDTH 550
but still I get the error:
register model requires that uvm_reg_data_width be defined as 550 or greater

Thanks,

Marc43
Marc43
Full Access
32 posts
November 11, 2020 at 4:24 am

In reply to AL_verif:

I guess I meant an appropriate place. I didn't manage to do it. Sorry.

Good luck

chr_sue
chr_sue
Full Access
3846 posts
November 11, 2020 at 5:33 am

In reply to AL_verif:

You cannot have a macro in a package. You have to to it in an application-specific macro file.

AL_verif
AL_verif
Full Access
16 posts
November 15, 2020 at 11:55 pm

I added it in the compilation command line,
and this passed!

-define UVM_DATA_WIDTH=550

Sv-hustler
Sv-hustler
Full Access
38 posts
March 16, 2022 at 10:13 am

I had a similar issue. From my environment point of view, I have declared 

//in sim.mk after Comp_Flags
Comp_Flags = -timescale 1ns/1ps \
+define+UVM_REG_DATA_WIDTH=256 \
//256 because my reg models were a max of 256 wide

Again this can be with respect to my env but the above has fixed the issue. I have tried declaring as `define and pass through the command which didn't work

When you do this you can see a info in log saying default value in Verilog class being overwritten .

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