Unable to compile a register model using registers of size 2048 bits

UVM
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1

Hello,

I am unable to compile my register model using registers of size 2048 bits. I know that the default size is 64 and we have to do

+define+UVM_REG_DATA_WIDTH=2048

when compiling UVM. But it doesn’t work.

It complains with the same error as before:

UVM_FATAL verilog_src/uvm-1.1d/src/reg/uvm_reg_block.svh(1093) @ 0: reporter [RegModel] Register model requires that UVM_REG_DATA_WIDTH be defined as 2048 or greater. Currently defined as 64

I am using QuestaSim. Maybe I am not compiling the UVM that I should compile, did you have this error? How did you solve it?

Thanks,
Marc

2

In reply to Marc43:

UVM_REG_DATA_WIDTH is a parameter used by the RAL. With +define+ you are specifying a macro but not a parameter. Best is to set UVM_REG_DATA_WIDTH in your RAL package to the correct value.

3

In reply to chr_sue:

In reply to Marc43:
UVM_REG_DATA_WIDTH is a parameter used by the RAL. With +define+ you are specifying a macro but not a parameter. Best is to set UVM_REG_DATA_WIDTH in your RAL package to the correct value.

Thank you for your reply. Then doing

`define UVM_REG_DATA_WIDTH 2048

at the top of my RAL package, should work?

It does not work for me.

4

In reply to Marc43:

No, this is again a macro.
In your RAL package do in a propriete place:

UVM_REG_DATA_WIDTH = 2048;
5

In reply to chr_sue:
I am not sure if that’s true. as far as I remember it was macro.

/uvm-1.2/src/reg/uvm_reg_model.svh:typedef  bit unsigned [`UVM_REG_DATA_WIDTH-1:0]  uvm_reg_data_t
uvm-1.1d/src/reg/uvm_reg_model.svh:typedef  bit unsigned [`UVM_REG_DATA_WIDTH-1:0]  uvm_reg_data_t ;

@Marc43 - you need to compile UVM source code with that define not your TB if that makes sense.

6

In reply to Vinay Jain:

You are right. It is amacro. Then you have to compile the RAL with respect to this macro using the define.

7

In reply to chr_sue:

Yes, it’s a macro. But how can you compile UVM with QuestaSim? I couldn’t, and I’ve tried a LOT of times. Any tutorial?

8

In reply to Marc43:

This forum is not for tool specific issues. Please consult your tools User Manual for instructions on compiling your simulation for UVM.

9

In reply to chr_sue:

In reply to Marc43:
No, this is again a macro.
In your RAL package do in a propriete place:

UVM_REG_DATA_WIDTH = 2048;

Where can I add it ?
could you please explain what do you mean “a propriate place” ?

I try to add it in my RAL package:
this way:
`UVM_REG_DATA_WIDTH = 550;
compilation failed.

I try to add in my package this way:
`define UVM_REG_DATA_WIDTH 550
but still I get the error:
register model requires that uvm_reg_data_width be defined as 550 or greater

Thanks,

10

In reply to AL_verif:

I guess I meant an appropriate place. I didn’t manage to do it. Sorry.

Good luck

11

In reply to AL_verif:

You cannot have a macro in a package. You have to to it in an application-specific macro file.

12

I added it in the compilation command line,
and this passed!

-define UVM_DATA_WIDTH=550

13

I had a similar issue. From my environment point of view, I have declared


//in sim.mk after Comp_Flags
Comp_Flags = -timescale 1ns/1ps \
+define+UVM_REG_DATA_WIDTH=256 \
//256 because my reg models were a max of 256 wide

Again this can be with respect to my env but the above has fixed the issue. I have tried declaring as `define and pass through the command which didn’t work

When you do this you can see a info in log saying default value in Verilog class being overwritten .