I am unable to compile my register model using registers of size 2048 bits. I know that the default size is 64 and we have to do
+define+UVM_REG_DATA_WIDTH=2048 when compiling UVM. But it doesn't work.
It complains with the same error as before:
UVM_FATAL verilog_src/uvm-1.1d/src/reg/uvm_reg_block.svh(1093) @ 0: reporter [RegModel] Register model requires that UVM_REG_DATA_WIDTH be defined as 2048 or greater. Currently defined as 64
I am using QuestaSim. Maybe I am not compiling the UVM that I should compile, did you have this error? How did you solve it?