Ubus environment design

Hi All,

I am a beginner in a UVM environment so I tried to debug the Ubus code which is given as an example in uvm 1.1d master.

I am confused at, in Environment, there are a master agent and slave agent as well dummy dut is present.in dummy dut, there are only input/outputs and FSM is provided. so in that environment, we verify what I mean Ubus master_dut or slave_dut?

till now I know that suppose we verify master RTL than we make testbench of slave and if we verify slave RTL then make a master testbench but if both master-slave and dut are present then we verify what.