Has anyone implemented the logic for monitoring the baud rate of UART? How we can do so ? If the baud rate deviates or the error is greater then 1% between the desired baud rate and achieved baud rate then it should give error.
In reply to jayati3108:
What you are describing is a typical application for SV Assertions. You should model your behavior in this way.
You can write an inline assertion assertion in baud generator block to check whether the baud_o is generated properly or not, instead of monitoring it using monitor.
In reply to shanthi:
ok , can we write like: -
lets say required baud rate = 100
allowable baud rate = 99,101 (coz 1% error is allowed)
99>=baud rate<=101
something like this
In reply to jayati3108:
The generation of baud_o depends on the divider latch register(DLR) value & the down counter. Once the value is loaded in DLR, the down counter gets loaded with DLR value & its keep decrementing every clock cycle, when the count becomes zero baud_o will be generated and again the counter will be reloaded back with the DLR value and process will continue.
You can write an assertion for checking the counter & baud_o generation based on above logic.
In reply to shanthi:
I think this is from design perspective. I dont have access to baud clock generation logic. I have to write in verification perspective.