Type Registration for following is Signed OR Unsigned?

UVM
,
1

For the following Code Snippet ::



class env #(BIT_WIDTH = 128) extends uvm_component;
 `uvm_component_param_utils(env#(BIT_WIDTH))
 ...
endclass

typedef  int  unsigned  UINT32  ;

class wrapper #(UINT32 BIT_WIDTH=256) extends uvm_component;  //   ALWAYS  Unsigned  Parameter  Irrespective  of  Sign  of  Final  Value  !!
 
 `uvm_component_param_utils( wrapper#(BIT_WIDTH) )  // [Q] Type  Registration  via  Signed  value  OR  Unsigned  Value  ??
 
  env #(BIT_WIDTH) e1;  //  BIT_WIDTH  would  be  unsigned  due  to  UINT32  .  Resolved  at  elaboration Time
 ...
 function void build_phase(uvm_phase phase);
  e1 = env#(BIT_WIDTH)::type_id::create("env1", this);
 endfunction
endclass

The macro gets ( `uvm_component_param_utils ) expanded at Compile - Time but the parameter resolution takes place at Elaboration Time

So will the Type Registration take place for wrapper class ( and env handle e1 ) at Elaboration Time where the value of
the parameter is resolved ( via Specialization ) ??

2

In reply to TC_2017:

Macros are just simple text substitution, they have little knowledge of the SystemVerilog syntax they generate. The `uvm_component_param_utils macro generates the line

 typedef uvm_component_registry#( wrapper#(BIT_WIDTH) ) type_id;

Since BIT_WIDTH is unsigned, the registration uses the unsigned specialization.