Type error

Hi,
I’m trying to implement a uvm scoreboard. While creating the uvm_analysis_imp and connect it with the monitor. I’m getting following error.
ERROR: formal and actual do not have assignment compatible data types on instance ‘top_tb.uvm_top_tb.test_i’ (expecting datatype compatible with ‘class uvm_pkg::uvm_port_base#(.IF(class uvm_pkg::uvm_tlm_if_base#(.T1(class agent_pkg::my_transaction),.T2(class agent_pkg::my_transaction))))’ but found ‘class uvm_pkg::uvm_analysis_imp#(.T(class test::my transaction),.IMP(class test::my_scoreboard))’ instead)

Sample code:

class my_scoreboard extends uvm_scoreboard;
  `uvm_component_utils(my_scoreboard)

  function new(string name="my_scoreboard", uvm_component parent=null);
    super.new(name,parent);
  endfunction

  uvm_analysis_imp#(my_transaction,my_scoreboard) a_export;

  function void build_phase(uvm_phase phase);		
    a_export = new("a_export",this);	
  endfunction:build_phase

  virtual function void write(my_transaction pkt);
  .
  .
  .
  endfunction
  .
  .
  .
  endclass

I’m connecting the agent’s monitor with scoreboard’s analysis_imp in my env’s connect phase as shown below.
monitor_inst.aport.connect(scoreboard_inst.a_export);

I’m getting the type error from the above line. Please help me to identify what mistake I’m doing here.

Thanks

In reply to Raj Guru:

Could you please show the declaration if yout monitor analysis port?

In reply to chr_sue:

class my_monitor extends uvm_monitor;
`uvm_component_utils(my_monitor)

uvm_analysis_port#(my_transaction)aport;

function new(string name=“my_monitor”,uvm_component parent);
a_port = new(“aport”,this);
endfunction

virutal task run_phase(uvm_phase phase);
aport.write(my_transaction);
.
.
endtask

endclass

In reply to Raj Guru:

In the monitor code you are not consistent with aport:

uvm_analysis_port#(my_transaction)aport;
a_port = new("aport",this);
aport.write(my_transaction);

In the constructor you do not call

super.new(name, parent);

In reply to chr_sue:

Hi chr_sue,
Thanks for the reply. a_port is a typo. Sorry!. My real issue is related to layered tb structure. Which I haven’t disclosed previously. In my tb I’m having a base monitor and driver. I’ve added the sample code below.


class monitor_base extends uvm_monitor;
  `uvm_component_utils(monitor_base)

  uvm_analysis_port#(my_transaction)aport;

  function new(string name="my_monitor",uvm_component parent);
    a_port = new("aport",this);
  endfunction

  virutal task run_phase(uvm_phase phase);
    .
    .
  endtask
endclass

class my_monitor extends monitor_base;
`uvm_component_utils(my_monitor)

  uvm_analysis_port#(my_transaction)aport;

  function new(string name="my_monitor",uvm_component parent);
    super.new(name,parent);
    aport = new("aport",this);
  endfunction

 virutal task run_phase(uvm_phase phase);
  aport.write(my_transaction);
  .
  .
 endtask

endclass

//Scoreboard code
class my_scoreboard extends uvm_scoreboard;
  `uvm_component_utils(my_scoreboard)
 
  function new(string name="my_scoreboard", uvm_component parent=null);
    super.new(name,parent);
  endfunction
 
  uvm_analysis_imp#(my_transaction,my_scoreboard) a_export;
 
  function void build_phase(uvm_phase phase);		
    a_export = new("a_export",this);	
  endfunction:build_phase
 
  virtual function void write(my_transaction pkt);
  .
  .
  .
  endfunction
  .
  .
  .
endclass

I’m connecting the ‘my_monitor’ class’s aport with ‘scoreboard’ class’s a_export. Whether this connection will cause the type error?

Please clarify this doubt.

Thanks

In reply to Raj Guru:

In my_monitor you have now 2 aports, one from the base monitor and another one from my_monitor. There is no need to declare the aport twice.
I’d recommend to clean-up your code having only 1 analysis port in your monitor.