Type of argument 'tmp_data__' of virtual method '__m_uvm_field_automation' in class 'cbc_seq' does not match with type of argument in the abstract superclass 'uvm_rgm_sequence'

UVM
,
1

Hi All,

I’m hitting with the follwing issue

“Type of argument ‘tmp_data__’ of virtual method ‘__m_uvm_field_automation’ in class ‘cbc_seq’ does not match with type of argument in the abstract superclass ‘uvm_rgm_sequence’”

from below shown contents of file

`ifndef CBC_SEQ__SV
`define CBC_SEQ__SV


`include "uvm_macros.svh"
import uvm_pkg::*;
import uvm_rgm_pkg::*;  
`include "uvm_rgm_sequence_macros.svh" // -*- FIXME include of uvm file other than uvm_macros.svh detected, you should move to an import based methodology


// Local defines for cell.
`define WIDTH_CBC_CLK_DIV  4
`define WIDTH_SLEEP_SEL    3
`define WIDTH_WAKEUP_SEL   3


class cbc_seq extends uvm_rgm_sequence;
  `uvm_object_utils_begin(cbc_seq) //bharath
 `uvm_object_utils_end
`uvm_declare_p_sequencer(uvm_rgm_sequencer) //bharath

  // Config settings for sequence.
  integer                           is_pscbc_cell = 0;
  integer                           wr_all = 1;
  string                            cbc_cfg_reg_st;
  

  // CBC cell register values.
  rand bit                           clk_enable;
  rand bit                           hw_control;
  rand bit [`WIDTH_CBC_CLK_DIV-1:0]  cbc_clk_divide;


  // PSCBC cell settings
  rand bit [`WIDTH_SLEEP_SEL-1:0]   cbc_sleep_val;
  rand bit [`WIDTH_WAKEUP_SEL-1:0]  cbc_wakeup_val;



  function new(string name="cbc_seq");
	super.new(name);
  endfunction : new


  //
  // Body task for sequence
  //
  extern virtual task body();


  //
  // Set sequence values (required for executing sequence).
  //
  extern virtual function void set_sequence_values(string cbc_reg_str,
						   integer is_pscbc = 0,
						   integer wr_all_fields = 1);

    
endclass : cbc_seq

//-----------------------------------------------------------------------------
// body
//-----------------------------------------------------------------------------
task cbc_seq::body();
  uvm_rgm_register_base m_reg_h;

    
  `uvm_info(get_type_name(), "//:- Start CBC register sequence()", UVM_LOW);

  //
  // After randomization, update register values with new values.
  //
    
  // Configuration register. All fields (CBC and PSCBC) are present in register,
  // so update all fields at one time.
  m_reg_h =   get_reg_by_name(cbc_cfg_reg_st);
  m_reg_h.set_field_value    ("f_clk_enable", clk_enable     );
  m_reg_h.set_field_value    ("f_hw_ctl",     hw_control     );

  if (wr_all == 1)
    begin
      m_reg_h.set_field_value    ("f_clk_div",    cbc_clk_divide );

      // PSCBC specific fields.
      m_reg_h.set_field_value    ("f_sleep",      cbc_sleep_val  );
      m_reg_h.set_field_value    ("f_wakeup",     cbc_wakeup_val );
    end
    
  `rgm_write_send(m_reg_h)
  get_response(rsp);

  // Read back to make sure write has completed.
  `rgm_read(m_reg_h)
  get_response(rsp);
    
endtask : body

  
//-----------------------------------------------------------------------------
// set_sequence_values
//-----------------------------------------------------------------------------
 function void cbc_seq::set_sequence_values(string cbc_reg_str,
					    integer is_pscbc = 0,
					    integer wr_all_fields = 1);

    cbc_cfg_reg_st = cbc_reg_str;
    is_pscbc_cell  = is_pscbc;
    wr_all         = wr_all_fields;
    
 endfunction : set_sequence_values 
   

`endif

I’m not getting what exactly error is poping up.

Please share your inputs to debug the error

note modeltech version using :10.5c
Thnaks,
koushik

2

In reply to koushik hk:

class cbc_seq extends uvm_rgm_sequence;
  `uvm_object_utils_begin(cbc_seq) <---- error is poping up from this point
 `uvm_object_utils_end
3

In reply to koushik hk:

The easiest fix is to not use the uvm_field_* macros.

4

In reply to koushik hk:

In reply to koushik hk:

class cbc_seq extends uvm_rgm_sequence;
`uvm_object_utils_begin(cbc_seq) <---- error is poping up from this point
`uvm_object_utils_end

Your sequnce definition misses the seq_item. It should be

class cbc_seq extends uvm_rgm_sequence #(uvm_seq_item);
  `uvm_object_utils_begin(cbc_seq)

Additionally I miss the following declaraions, needed for register access:

  rand  uvm_reg_data_t data;         // For passing data
  uvm_status_e         status;       // Returning access status
5

In reply to chr_sue:

Hi chr_sue,

actually uvm_rgm_sequence class extended from uvm_sequence#(uvm_rgm_reg_op)

so i’m directly extending cbc_seq class from uvm_regm_sequence.

so do i need to again use #(uvm_rgm_reg_op) form uvm_reg_sequence class.

thanks,
koushik

6

In reply to koushik hk:

so i’m directly extending cbc_seq class from uvm_rgm_sequence

its typo here.

thanks,
koushik

7

In reply to koushik hk:

The definition of uvm_reg_sequence is like this:

class uvm_reg_sequence #(type BASE=uvm_sequence #(uvm_reg_item)) extends BASE;

That means uvm_reg_sequence is parameterized and you have to use another factory registration macro.

BTW I have never seen the uvm_sequence in practice. Even the UVM Cookbook does not show this. All projects using a definition as I have shown above:

class cbc_seq extends uvm_rgm_sequence #(uvm_seq_item);
  `uvm_object_utils_begin(cbc_seq)
8

In reply to chr_sue:

They are using uvm_rgm_sequence, which is not part of the standard UVM.

9

In reply to dave_59:

This was my fault. I meant:

class cbc_seq extends uvm_sequence #(uvm_seq_item);
  `uvm_object_utils_begin(cbc_seq)
10

Hi All,

Thanks for your replies, actually i was recompiling uvm_pkg.sv file, so these errors are poping up.so after removing uvm_pkg.sv for recompilation issues got resloved.

Thanks,
koushik