[1] LRM 18002 5.5.2.14 connect ::
b) The provider’s interface type (blocking, non-blocking, analysis, etc.) shall be compatible, e.g., an
uvm_blocking_put_port #(T) is compatible with an uvm_put_export #(T) and
uvm_blocking_put_imp #(T) because the export and imp provide the interface required
by the uvm_blocking_put_port
However when I try the same ::
`include "uvm_pkg.sv"
`include "uvm_macros.svh"
import uvm_pkg::*;
class trans extends uvm_transaction;
rand int addr;
rand int data;
rand bit write;
endclass
`define COMP_NEW function new ( string name , uvm_component parent ) ; \
super.new(name,parent);\
endfunction
class leaf1 extends uvm_component;
`uvm_component_utils(leaf1)
uvm_blocking_put_port #(trans) port;
`COMP_NEW
virtual function void build_phase(uvm_phase phase);
port = new("port",this);
endfunction
virtual task run_phase(uvm_phase phase);
trans t;
phase.raise_objection(this, "prolonging run_phase");
t = new;
t.randomize();
port.put(t);
phase.drop_objection(this, "prolonging run_phase");
endtask
endclass
typedef class leaf2 ;
class comp1 extends uvm_component;
`uvm_component_utils(comp1)
uvm_put_export #(trans) out; // Changed from blocking_put_export TO put_export !!
leaf2 leaf2_h ;
`COMP_NEW
function void build_phase(uvm_phase phase);
out = new("out",this);
leaf2_h = new("leaf2_h",this);
endfunction
virtual function void connect_phase(uvm_phase phase);
out.connect(leaf2_h.imp);
endfunction
endclass
class leaf2 extends uvm_component;
`uvm_component_utils(leaf2)
uvm_blocking_put_imp #(trans,leaf2) imp ;
`COMP_NEW
function void build_phase(uvm_phase phase);
imp = new("imp",this);
endfunction
virtual task put(trans t);
$display("Got trans: addr=%0d, data=%0d, write=%0d",t.addr, t.data, t.write);
endtask
endclass
class env extends uvm_component;
`uvm_component_utils(env)
comp1 comp1_h;
leaf1 leaf1_h;
`COMP_NEW
virtual function void build_phase(uvm_phase phase);
comp1_h = new("comp1_h",this);
leaf1_h = new("leaf1_h",this);
endfunction
// NOTE :: Will this work ??
virtual function void connect_phase(uvm_phase phase);
leaf1_h.port.connect(comp1_h.out);
endfunction
endclass
module TOP ;
initial begin
run_test("env");
end
endmodule
I Observe run-time error ::
UVM_ERROR @ 0: uvm_test_top.comp1_h.out [Connection Error] uvm_test_top.comp1_h.leaf2_h.imp (of type uvm_blocking_put_imp)
does not provide the complete interface required of this port (type uvm_put_export)
[2] UVM Class Reference Manual 1.2 ,
21.5 TLM Implementation Port Declaration Macros ::
//Define two new put interfaces which are compatible with uvm_put_ports
//and uvm_put_exports.
`uvm_put_imp_decl(_1)
`uvm_put_imp_decl(_2)
class my_put_imp#(type T=int) extends uvm_component;
uvm_put_imp_1#(T,my_put_imp#(T)) put_imp1;
uvm_put_imp_2#(T,my_put_imp#(T)) put_imp2;
...
function void put_1 (input T t); // Return type should be bit I believe
//puts coming into put_imp1
...
endfunction
function void put_2(input T t); // Return type should be bit I believe
//puts coming into put_imp2
...
endfunction
endclass
This however would give compile-time error as user doesn’t provide implementation for
(1) task put( T t ) ; (2) function bit can_put( T t ) ;