Time out

Hi All
I suffer this error reporter [PH_TIMEOUT] Explicit timeout of 1000000 hit, indicating a probable testbench issue

it seem is phase time out, how can i know which phase is time out, and what commponent make this time out?

what is the meaning of timeout of 1000000 hit. how can i modify the value of hit??
thanks !!

https://verificationacademy.com/forums/uvm/uvmfatal-default-timeout-9200-hit-indicating-probable-testbench-issue