Time elapsing and hardware mirroring in RAL

UVM
1

Hello,

I have a fundamental question about using RAL.

In the reference, The general sequence task can be repleaced to RAL sequence as below.


//General Sequence task
virtual task body();
 `uvm_do_with(req, {addr==’h0; kind==UMV_READ;});
 `uvm_do_with(req, {addr==’h4009; data==’1; kind==UVM_WRITE;});
endtask

// RAL Sequence
virtual task body(); uvm_status_e status; uvm_reg_data_t data;
  regmodel.HOST_ID.read(status, data, .parent(this)); // can specify .path
  regmodel.RAM.write(status, 9, ’1, .parent(this)); // defaults to frontdoor
endtask

The general sequence task consumes time duration (clocks) for bus signaling to read/write data.
However RAL sequence dess not consume the time, since it calls functions by regmodel adapter and regmodel.
Then how we verify the acutal read/write bus operation and time dependant simulation flags in RAL?

2

In reply to uvmbee:

Your observation is incorrect.
No sequence is consuming time. Any timing is related to the driver/monitor.
And you do not simply replace the standard sequence with a register sequence. The register sequence needs a converter, provided by the register adapter.