Is there a way to define register model(containing two maps) and three memory models in a single uvm_reg_block instance

UVM
,
1

I am looking for a way to define following items in a top level memory model

  1. register model - which has two maps
  2. 3 memory models - which has different base address

I want to define them in a top level model.

I looked at UVM examples in UVM 1.2 package but could not find it. Can you please explain me how this is feasible ?

2

In reply to vm16:

Have a look to the ‘Memory Example’ in the code examples of the UVM Cookbook.

3

In reply to chr_sue:

In reply to vm16:
Have a look to the ‘Memory Example’ in the code examples of the UVM Cookbook.

Thanks, I could set up this way.
Top level
spi_map
ahb_map
spi_map.add_submap(reg_model.spi_map)
ahb_map.add_submap(reg_model.ahb_map)
Register model
spi_map
ahb_map