I have been trying to understand sequence from test in UVM,
I would came across test class as the below,
This example looks like “start” used for running sequencer.
but as you can see,
In build_phase, only implemented with sequence. No sequencer
In connect_phase, only implemented with sequencer. No sequence
1.Is this normal usage for implementing? Probably, It has something meaning.
2.Is this possible way to implement as the below?
I want to know that why does it need to implement “pp_seqr = tb.pp.tx_agent.sequencer;” in connect_phase? I think it equivalent as the below. Also, “pp_tx_sequencer pp_seqr;” declare no necessary.
task run_phase(uvm_phase phase);
pp5.start(tb.pp.tx_agent.sequencer);
endtask : run_phase
class seq_from_test extends base_test;
// component macro
`uvm_component_utils(seq_from_test)
pp_tx_sequencer pp_seqr;
pp_5_packets pp5;
// component constructor
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new
function void build_phase(uvm_phase phase);
pp5 = pp_5_packets::type_id::create("pp5", this);
super.build_phase(phase);
endfunction : build_phase
function void connect_phase(uvm_phase phase);
pp_seqr = tb.pp.tx_agent.sequencer;
endfunction : connect_phase
task run_phase(uvm_phase phase);
pp5.start(pp_seqr);
endtask : run_phase
endclass : seq_from_test