Testing RTL design

UVM
,
1

one of my interviewer asking below question
What is the most common reason why bugs are missed during the testing of the RTL design?
i am unable to answer to the above question.please provide the solution?

2

In reply to anvesh dangeti:

This is a trick question. Not being able to answer this question is the most common reason why bugs are missed during the testing of the RTL design.

There is no correct answer to this question; the interviewer is just fishing for ideas that show you have some experience. Everyone’s experience will be different. Sone ideas i can think of:

  • No testplan. Did not review the requirements to plan out what to test
  • Insufficient requirements.
  • Not enough time spent on verification
  • Same engineer does verification of what they designed
3

This is a million dollar question … Nice answer

dave_59

I can add couple of points …

  • There could be a Testplan but incomplete. Basically not fully thought through all the cases…
  • Shared Bias of designer and DV though they are two different people but may have common bias due to their interactions… this should be caught in the review …

Siva