Hello everyone,
I am actually working on implementing a testbench in an FPGA. I am using a SmartFusion 2, does anyone know Libero well enough to help me with SystemVerilog use on Libero ? What is the accurate flow to use to design an UVM ? What are the parts of my design that are standards ? What do I redesign ? How many agents do I use ? When I am using many agents, is there a way to synchronise them all ?
I have so many questions but then I am not familiar with UVM, I am learning bit by bit. I already am thinking about many other questions too, but for now getting those answers would be amazing.
In reply to selmenna:
The key question is: why do you Need a synthesizable testbench, putting this into a FPGA?
It is more complicated as using the Standard UVM.
You might find answers here: SystemVerilog Testbench Acceleration | Acceleration | Verification Academy
Why ? Because FPGA’s calculators are faster than the computer’s. I need to accelerate my test bench in order to have a better coverage.
In reply to selmenna:
As of today, you cannot synthesize any class based objects into an FPGA. So that means no UVM testbench. There are ways of getting a UVM testbench to communicate with an FPGA, you should talk with your tool vendors for a solution.
In reply to selmenna:
You make me smiling, acceleration and high functional coverage does not have a relationship. And a UVM testbench is not really slowing down your simulation.
In reply to dave_59:
What if I had an SOC ? Class based objects may be synthesized into the microprocessor while the rest goes into the FPGA. Would that work ? Either way how does UVM emulation work ? Doesn’t it use hardware ?
In reply to chr_sue:
The thing is not we were not using UVM testbenches before. And my researches pushed me into those conclusions :
- An all-in-all software testbench is slower than an emulated one.
- It can be accelerated by moving some parts into hardware.
As of the coverage, what I meant is that in here the simulations and verification tests on motors are taking too long (around a whole day) so we can never intend to verify the system using an exhaustive list of stimulises. That’s the point. Accelerating the tests would enable the use of much more stimulises.
In reply to selmenna:
There are a few question I’d like to ask:
(1) How do you synthesize clas-based objects into hardware?
(2) Emulation is using a very specific Approach synthesizing certain objects, but not all. The problem is how to synchronize these parts. The emulator is providing its own mechanism.
If your simulation runs so long this is definitely not caused by your UVM testbench. It is the RTL which is running so slow. This cannot be accelerated by passing certain TB elements into hardware.
To solve the speed problem you should think about other approaches like increasing you clock frequency on the RTL side.
In reply to chr_sue:
I do not know how to do so, this is what this topic is for.
Either way, I got some answers from an expert before and he mentionned that I would need to re-write the standards to be able to implement them on my FPGA.
But, the response he gave wasn’t sufficient.
In reply to selmenna:
You could put your RTL into a FPGA. Then you have to check with your Simulator Provider if the Simulator can communicate with the FPGA on the on Hand ond the UVM testbench on the other hand.
In reply to chr_sue:
I contacted the vendor, I am waiting for an answer.
Thank you, still I need answers to my other questions :
What is the accurate flow to use to design an UVM ? What are the parts of my design that are standards ? What do I redesign ? How many agents do I use ? When I am using many agents, is there a way to synchronise them all ?
In reply to selmenna:
OK, I see you are a newbee in UVM :-)
There is no ONE flow to do this. But there are a few guidelines you should follow. I see 2 approaches:
(1) you should take part in a UVM Course if you are familiar with SystemVerilog.
(2) If you have time you can exercise the UVM on your own. Visit Doulos KnowHow.
There you’ll find a lot of important stuff.
In reply to chr_sue:
I am a newbee for sure. I’ve taken time to go through some tutorials and I have gotten more familiar with System Verilog. The Oriented Object Programmation is not that scaring to me, I am a C++ pro. But, still I need help with UVM.
The link will definitely help. I will go through the Courses before the end of the week. And I’ll be back again with questions this week-end probably. ;)
Thank you.