Test in run_phase and monitor in main_phase

UVM
,
1

Hi ,

I have recently started with UVM phases and have a basic question .


class my_monitor extends uvm_monitor ;

 `uvm_component_utils(my_monitor)

  
 // Standard 3-line Constructor

  virtual task main_phase ( uvm_phase phase ); 
  
     phase.raise_objection(this) ;
     $timeformat(-9,3,"ns",8); 
	 #10ns ;
	 `uvm_info(get_type_name(),$sformatf(" %0t %0s:: main_phase() done ",$time,get_name()),UVM_NONE)

	 phase.drop_objection(this) ;
  
  endtask  

endclass

class test extends uvm_test ;

 `uvm_component_utils(test)
 
 // Standard 3-line Constructor
  
  my_monitor m_monitor ;

  function void build_phase ( uvm_phase phase ) ;
     m_monitor = new("m_monitor",this);
  endfunction

  virtual task run_phase ( uvm_phase phase ); 
  
     phase.raise_objection(this) ; 
     $timeformat(-9,3,"ns",8); 
     
	 #5ns ;
	 `uvm_info(get_type_name(),$sformatf(" %0t %0s:: run_phase() done ",$time,get_name()),UVM_NONE)

	 phase.drop_objection(this) ;
  
  endtask  

endclass 



initial begin

  run_test("test") ;

end

I see following Output ::

UVM_INFO @ 0: reporter [RNTST] Running test test…
UVM_INFO @ 0.000ns: uvm_test_top [test] 0.000ns uvm_test_top:: run_phase() done
UVM_INFO @ 0.000ns: reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase
UVM_INFO @ 0.000ns: uvm_test_top.m_monitor [my_monitor] 0.000ns m_monitor:: main_phase() done

Need help with how the above code works .

I understand that run_phase starts parallel to pre_reset phase .

[1] Since I don’t have reset N configure in monitor shouldn’t run_phase of test run parallel to main_phase of monitor .

[2] Shouldn’t run_phase of test finish at 5 ns ? . In output I see run_phase is done at 0ns . How ?

[3] I purposely gave a delay in monitor greater than test so that the task based phases finish after monitor has dropped objection .
Is there a way to drop objection after monitor completes ( by using mixture of run && main phase ) ?

Thanks ,
ABD

2

In reply to ABD_91:

I’m not getting the same result as you are with any simulator on EDAPlayground. It would have helped to add the 4 extra lines to have a complete runnable example.

I’m seeing

# UVM_INFO @ 0: reporter [RNTST] Running test test...
# UVM_INFO testbench.sv(44) @ 5.000ns: uvm_test_top [test]  5.000ns uvm_test_top:: run_phase() done 
# UVM_INFO verilog_src/uvm-1.2/src/base/uvm_objection.svh(1270) @ 5.000ns: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# UVM_INFO testbench.sv(19) @ 10.000ns: uvm_test_top.m_monitor [my_monitor]  10.000ns m_monitor:: main_phase() done 
# UVM_INFO verilog_src/uvm-1.2/src/base/uvm_report_server.svh(847) @ 10.000ns: reporter [UVM/REPORT/SERVER]

We strongly recommend just sticking with the run_phase and instead use sequences to manage order of behaviors. If you insist on using the sub-phases, don’t mix with the run_phase. Use only the run_phase for components that do not care about phases.