this is dual clock asynchronous FIFO based FIFO generator IP .
actuatly i facing proble in interface class we need to take both write_clk,read_clk or single clock.
i planned like that:
1) one write agent:w_driver,w_monitor,w_sequencer;
2)one read agent:r_driver,r_monitor,r_sequencer ;
but in interface like : interface interface_name(input bit clk);//here what should i do
because IP design working based on write_clk,and read_clk.
if you will guide me its my pleasure.