In reply to saritr:
In SystemVerilog, a task call may block and consume time, whereas a function must execute and return in 0 time.
The build and connect phases are part of the setup and configuration of your simulation and all must be completed before time can advance. The phases after the run_phase are also functions because after the completion of your test, there should be no more consumption of time.
Another way to think of it is the run_phase is solely for exercising your DUT by simulating and monitoring through its interfaces, and the phases before and after the run_phase is just for management of the testbench.