Task calling in sequence /Test

UVM
1

Hi,

we have AXI slave tasks in .sv file that will communicate with our DUT .

eg : task write () ; read() ;

It is used to work fine in system Verilog test bench approach ,now we shifted to UVM methodology ,how we can integrate this or how we can use in sequence or test case ,so that using “write” task we need to configure DUT then we need to start our driver .

Thanks
Chethan M

2

Any code example will be Good

3

In reply to chethan malleshappa1:

Please see my DVCon Paper: The Missing Link: The Testbench to DUT Connection

4

Thanks for reply

I am reframing my question:

Below Task present in DUT :
master_agent.AXI4LITE_WRITE_BURST(base_addr + addr,0,data,resp);

I want to write it from sequence/Test case ,above solution is applicable still?

5

In reply to chethan malleshappa1:

Yes. Instead of the probe() method in the paper, change it to AXI4LITE_WRITE_BURST.