SystemVerilog Scheduler and UVM Phases

UVM
1

Hello Forum,

Kindly help me in clarifying the doubt regarding the SV scheduler and UVM phases.

We understand that UVM environment have many SV keywords or logic like coverage,assertions sv logic etc. When we run the uvm environment, how the uvm phases(build, connect, eoe,sos,run, extract etc) and sv scheduler(containing preponed, active, inactive, observe etc) interact with each other. Is it making some sense or both are already sync to each other in background. Please help.

Thanks and Regards
Sunil Sharma

2

In reply to sunils:

The SV Scheduler and the UVM phases are 2 complete different Things. The Scheduler defines how the assifmnets,assertions etc. are executed in a certain time step. Thze phasing in UVM is related to construct a complete UVM testbench, run tests an eevaluate the results.