Syntax error

UVM
1

i dont find any syntax error here but its showing something like this

Error-[SE] Syntax error
Following verilog source has syntax error :
“dpram_test.sv”, 7: token is ‘dpram_base_test’
class dpram_test extends dpram_base_test;
^

The following EDA playground link of that

2

In reply to yethishwar:

Hi Yesthiswhar,

It seems the file containing the base class ‘dpram_base_test’ is not compiled before dpram_test.sv.

You need to order the files rightly for compilation.

Thanks,
Prem

3

In reply to yethishwar:

It means, your dpram_test.sv doesn’t see dpram_base_test class. Please include dpram_base_test file to dpram_test.sv file.


`include "dpram_base_test.sv"

This is simple error. Please try to self-debug the problem first, before asking the solution.

4

In reply to chris_le:

Thank you sir for your advice .I debugged it before posting the question .but as i am new to this field , i was unable to identify the error .