Hi All,
How do i make checker for synchronous memory in UVM environment?
In reply to Mukund Sojitra:
Hi All,
How do i make checker for synchronous memory in UVM environment?
Have you thought of putting the checker in an interface? Below is code for an example extracted from my SVA Handbook 4th Edition; it may help you as a guide or as ideas.
If you need the checker to be within a task, consider using tasks for your assertions; see PAPER: Understanding the SVA Engine + Simple alternate solutions - SystemVerilog - Verification Academy
module memory_data_integrity_check (
input bit write, // memory write
input bit read, // memory read
input bit[31:0] wdata, // data written to memory
input bit[31:0] addr, // memory address -- small for simulation
input bit reset_n, // active low reset
input bit clk); // clock
timeunit 1ns; timeprecision 100ps;
default clocking cb_clk @ (posedge clk); endclocking
int mem_aarray[*]; // associative array (AA) to be used by property
bit [31:0] rdata; // data read from memory
bit mem_aarray_exists; // exists at specified address
assign mem_aarray_exists = mem_aarray.exists(addr);
always_comb
if(mem_aarray_exists)
rdata = mem_aarray[addr]; //
always@ (posedge clk)
if (reset_n==1'b0) mem_aarray.delete; // Clears AA elements
else if (write) mem_aarray[addr] = wdata; // store data
property p_read_after_write;
bit [31:0] v_wrdata, v_wraddr;
(write, v_wraddr=addr, v_wrdata= wdata) |-> // if write, save data and addr
(read && mem_aarray_exists && addr==v_wraddr) [->1] |-> // @read and data there at same written addr
rdata==v_wrdata; // read data is same as what was written
endproperty : p_read_after_write
ap_read_after_write : assert property (p_read_after_write)
$info("addr =%h, rdata=%h", $sampled(addr), $sampled(rdata)); else
$error("addr =%h, rdata=%h", $sampled(addr), $sampled(rdata));
property p_read_before_write;
not (read && !mem_aarray_exists); // never a read on an non written address
endproperty : p_read_before_write
ap_read_before_write : assert property (p_read_before_write);
endmodule : memory_data_integrity_check
class c_xactn;
rand bit write; // memory write
rand bit read; // memory read
rand int wdata; // data written to memory
rand bit[31:0] addr; // memory address
constraint addr_range_cst { addr <= 15 ;}
constraint no_wr_and_rd_cst { !(read && write);}
endclass : c_xactn
module top;
timeunit 1ns; timeprecision 100ps;
bit write; // memory write
bit read; // memory read
int wdata; // data written to memory
int rdata; // data read from memory
bit[31:0] addr; // memory address
bit reset_n=1'b1; // active low reset
bit clk=1'b1; // clock
c_xactn c1=new();
memory_data_integrity_check mem_check1 (.*);
initial forever #50 clk=!clk;
always_ff @ (posedge clk) begin
if(!c1.randomize()) $error("c1 randomization failure");
write <= c1.write;
read <= c1.read;
wdata <= c1.wdata;
addr <= c1.addr;
end
endmodule : top
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115
Hi ben,
thank you very much for your kind help.
Hi,chr_sue
I don’t know what to check .
You please suggest me.
In reply to Mukund Sojitra:
Hi,chr_sue
I don’t know what to check.
You please suggest me.
Your original post was How do i make checker for synchronous memory ?
I presumed that what you meant was:
- I have a large memory.
- I need to check that it works, meaning that what I read is indeed what I wrote. The model I gave you does that.
- What are your requirements? Access speed? Size? Refresh rate (if dynamic mem), …
YOU need to specify what you want.
Sorry to be so blunt, but I don’t know what to check. sounds more like I don’t know what I want, I need, and what the hell I am doing. I don’t know my requirements Not a good starting point to “what to check”. You better do better than that.
Please, don’t take offense, but people who know me *and I provided many reviews, papers and books)*understand that I tend to be very blunt and straight in my comments.
Ben SystemVerilog.us
Hi Ben,
Thanks for guiding me. I want do protocol checking that whatever data i am writing in memory is actually written or not?
In reply to Mukund Sojitra:
Then write assertions (In SVA (if in interface or module or SV checker) or in tasks (if within a class)) that check for the protocol interfaces. You may also use associative array, as described in my model to emulate a very large memory. You should have a document that defines the protocol requirements. Assertions basically check that the requirements are met, based on those requirement documents, and not on the implementation, obviously.
Ben SystemVerilog.us
Thank you.