Synchronizing between Driver and Monitor in the same agent

UVM
1

Hi,
in the “uvm_basics_complete.sv” code of Mentor the driver and the monitor work together in posedge clock .

In Driver :

 task run_phase(uvm_phase phase);
      forever
      begin
        my_transaction tx;
        @(posedge dut_vi.clock);
        seq_item_port.get(tx);

In Monitor:

task run_phase(uvm_phase phase);
      forever
      begin
        my_transaction tx;
        @(posedge dut_vi.clock);

The Question is if both driver and monitor works in posedge clk , how can i ensure the monitor detects the changes in the IF
directly after the driver puts them ?
Another question is why in driver, they are using blocking assignments when the “rule” using non blocking assignment in driver ?
Thanks