SV interface - parameter vs local signal

UVM
,
1

is there any difference when clock for an interface is defined through interface parameter versus when it is a part of interface signals, like the one below:

interface DUT_intf ();
logic clock;
...
endinterface

interface DUT_intf (input clock);
...
endinterface
2

In reply to verif_learner:

The difference is whether you want the interface to have an independent clock, or share the signal from some other source that you connect to the interface port. BTW, the proper terminology is port — a parameter means something else in SystemVerilog.

3

In reply to dave_59:

Thanks. I am not clear what you mean by independent clock vs share the signal.
An example will help.

4

In reply to verif_learner:

Interface ports work the same as module ports — they make connections. In the example below, top.i1.clock, top.i2.clock, and top.i3.clock always have the same value driven by top.clk.

interface DUT_intf (input bit clock);
...
endinterface

module top;
bit clk;
DUT_intf i1(clk);
DUT_intf i2(clk);
DUT_intf i3(clk);
...
endmodule

In the example below, top.i1.clock, top.i2.clock, and top.i3.clock may be driven independently.

interface DUT_intf ();
bit clock...
endinterface

module top;
bit clk;
DUT_intf i1();
DUT_intf i2();
DUT_intf i3();
...
endmodule