Hello,
Let’s say there is uvm_component A. B inherits from A. I would like to modify run_phase of B, but don’t want to change B.
I create C, which inherits from B, and override B with C.
run_phase of C overwrites the run_phase of B.
run_phase of B uses super.run_phase().
I can’t do super.run_phase() in C because it will call the run_phase of B as opposed to run_phase of A.
At the same time super.super.run_phase() isn’t supported by SystemVerilog.
What is the right way to solve this?
In reply to dave_59:
Is this supported by standard?
I was assuming such option is possible only for static functions.
Can you please explain little bit more.
In reply to haykp:
Accessing static members is only one of many uses of the Scope Resolution Operator. See section 8.23 in the 1800-2017 LRM.
In reply to dave_59:
Reviving this thread.
I tried to do this:
virtual task main_phase(uvm_phase phase);
uvm_env::main_phase(phase);
endtask
This is the error message, which I get:
Scoped reference to the non-static class task/function
‘uvm_component::main_phase’ is not allowed.
Does the message make sense?