Let's say there is uvm_component A. B inherits from A. I would like to modify run_phase of B, but don't want to change B.
I create C, which inherits from B, and override B with C.
run_phase of C overwrites the run_phase of B.
run_phase of B uses super.run_phase().
I can't do super.run_phase() in C because it will call the run_phase of B as opposed to run_phase of A.
At the same time super.super.run_phase() isn't supported by SystemVerilog.
What is the right way to solve this?