Stringing together multiple models to generate stimulus and checking

We have a bunch of individual module tests where each module has a UVM reference model with an analysis port in and out (or many in/ many out). It uses our universal defined data type that we extend from uvm_transaction. Our drivers and monitors are working fine. We have a common environment that we pass and our environment gets built for many modules. So far, very good. Lots of reuse.

We have a base class for our model and use a factory override for each test. Much less code to maintain.

What we would like to do is have the models “strung together” in order to be able to reuse them in order to generate stimulus.

Say for example, I have a module “modulator”. I can generate pretty random data and have it modulate and check the data against the modulate model and get lots of coverage.

Now, let’s say I want to test “demodulate”. I need to generate a more complex waveform which modulates the signal. I want to reuse the modulate model which has an analysis port in, and analysis port out. I might want to string another model to generate noise on the signal.

I cannot really do this in sequence because it gets created in one phase.

On a previous program, we achieved this by embedding the models into the driver and connected them all there. I am not sure that is a great approach. The sequence should be creating the stim. We also have used the DPI to get stimulus and models from C and Matlab.

For those who have UVM Systemverilog models of each block: How are others doing this? I can think of a plethora of ways but none of them seem really clean and reusable…