Stop and restart assertion from sequence

Is there a way to stop and restarts assertions from the uvm sequence.

I have a testbench requirement where in the middle of a sequence there is a dirty period,where the assertions are expected to fail. I want to disable
all the assertions (under testbench heirarchy) during this dirty period and enable it again after this dirty period is over.

I tried adding following in my sequence, but it gave error
$assertoff(1,uvm_test_top.testbench);

$assertoff(1,testbench);

*The name (‘uvm_test_top.testbench’) was not found in the current scope. Please verify the spelling of the name ‘uvm_test_top.testbench’

** Error (suppressible): …/…/…/…/verification/testcases/sequences/axi_rgm_seq_lib_hdmi_2_1_b2b.sv(8943): (vlog-7027) The name (‘testbench’) was not found in the current scope. Please verify the spelling of the name ‘testbench’.*

Could you please advice on what should be my approach for this requirement.

Thanks in Advance.

In reply to jerin:

Assertions are always signal- related. Defining a property/assertion allows you to switch-off thhe evaluation for certain periods using a corresponding signal.
The construct is

disable iff(your_signal).

As far as the value of your signal is high the evalution of your property is suppressed.

A reasobale solution would be to generate ‘your_signal’ in your driver, depending on a special indication in your seq_item.

In reply to chr_sue:
Thanks chr_sue.
I will try it out.