Hi,
I want to start the sequence without start method means by using default sequence in router.
Below one is my sequence
class good_pkt_wr_xtn extends router_wbase_seq;
`uvm_object_utils(good_pkt_wr_xtn)
extern function new(string name = "good_pkt_wr_xtn");
extern task body();
endclass
function good_pkt_wr_xtn::new(string name = "good_pkt_wr_xtn");
super.new(name);
endfunction
task good_pkt_wr_xtn::body();
$display($time,">>>>>>>>>>>>>>>>>>>>>>>DEFAULT SEQUENCEC>>>>>>>>>>>>>>>>>>>");
if(starting_phase != null)
starting_phase.raise_objection(this,"start_of_default_sequence");
repeat(10) begin
req = write_xtn::type_id::create("req");
start_item(req);
assert(req.randomize() with {xtn_type==GOOD_XTN ;} );
`uvm_info("ROUTER_GOOD_PKT_WR_SEQUENCE",$sformatf("printing from sequence \n %s", req.sprint()),UVM_NONE)
finish_item(req);
if(starting_phase!=null)
starting_phase.drop_objection(this,"end_of_default_sequence");
endtask
This is my test
class router_wr_vseq_test extends router_base_test;
`uvm_component_utils(router_wr_vseq_test)
// router_good_pkt_vseq router_seqh;
good_pkt_wr_xtn router_seqh;
good_pkt_rd_xtn rd_seq;
extern function new(string name = "router_wr_vseq_test" , uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
endclass
function router_wr_vseq_test::new(string name = "router_wr_vseq_test" , uvm_component parent);
super.new(name,parent);
endfunction
function void router_wr_vseq_test::build_phase(uvm_phase phase);
super.build_phase(phase);
router_seqh=good_pkt_wr_xtn::type_id::create("router_seqh");
//uvm_config_db #(uvm_sequence_base)::set(this,“router_envh.wagt_top.agnth[0].m_sequencer.main_phase”,“default_sequence”,router_seqh);
$display(" LAKSHMAN++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++LAKSHMAN");
uvm_config_db #(uvm_object_wrapper)::set(this,“router_envh.ragt_top.agnth[0].m_sequencer.main_phase”,“default_sequence”,good_pkt_wr_xtn::type_id::get());
uvm_config_db #(uvm_object_wrapper)::set(null,“router_envh.ragt_top.agnth[0].m_sequencer.main_phase”,“default_sequence”,good_pkt_wr_xtn::type_id::get());
// uvm_config_db#(uvm_sequence_base)::dump();
endfunction
task router_wr_vseq_test::run_phase(uvm_phase phase);
phase.raise_objection(this);
//$display(“==========%p=======”,good_pkt_wr_xtn::type_id::get());
$display($time,">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>START OF RUN_PHASE<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
#1;
//$display(“==========%p=======”,good_pkt_wr_xtn::type_id::get());
//.start(router_envh.wagt_top.agnth[0].m_sequencer);
//router_seqh.start(router_envh.wagt_top.agnth[0].m_sequencer);
#1000;
$display($time,“>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>END OF RUN_PHASE<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<”);
phase.drop_objection(this);
endtask
can any one tell whether is is setting or not.
It is not entering into body task in sequence.