Some unexpected result about the uvm_top.set_timeout() funtion

UVM
,
1

firstly, i set uvm_top.set_timeout(2000,0) in build_phase , expected the sim will end at 2000ns (timescale 1ns/1ps)

but when i set timescale 1ps/1ps for vcs compile command , the sim end at 2000ps

why this happend ?

2

In reply to Achilles:

https://verificationacademy.com/forums/uvm/regd.-time-unit-settimeout-call