SOC level UVM testbench,

hello Seniors,

i am new in SOC level ,
please let me know what is majoe diffrence between Normal UVM testbench and SOC level UVM testbench .

Thanks & Best Regards
Shubham

In reply to uvm_verification:

Both are UVM testbenches. The main difference is the SoC level testbench will consist of block level testbenches. They should be reused on the SoC level.

sir ,
i am thinking in this manner like SOC contain 5 blocks, than for this we will create 5 environment classes and all 5 environment classes create in side test class and then in TOP module call run_test is it correct approch or not .

In reply to uvm_verification:

No you’ll create a top env which contains the sub envs. This top_env will be instantiated in the test class.

In reply to chr_sue:

In reply to uvm_verification:
No you’ll create a top env which contains the sub envs. This top_env will be instantiated in the test class.

Thanks sir