How can you implement a simulation timeout mechanism using UVM methodology?
In reply to anvesh dangeti:
On the command line.
https://verificationacademy.com/forums/uvm/heartbeat-monitor-vs-watchdog-timer
How can you implement a simulation timeout mechanism using UVM methodology?
In reply to anvesh dangeti:
On the command line.
https://verificationacademy.com/forums/uvm/heartbeat-monitor-vs-watchdog-timer