Simulation shows req and rsp have null values

Hello Forum,

I am verifying simple dut with uvm-1.1d and Questasim-10.2b. In the simulation it shows the following error:

# UVM_INFO @ 0: reporter [RNTST] Running test test...
# UVM_INFO test.sv(20) @ 0: uvm_test_top [addition test] 
# ---------------------------------
# Name    Type         Size  Value 
# ---------------------------------
# mseq    my_sequence  -     @720  
#   knob  integral     32    'h19  
#   req   object       -     <null>
#   rsp   object       -     <null>
# ---------------------------------
# 
# UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1268) @ 52400: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase

Can you please help in this regard, what can be the possible reason.

Thanks and Regards
Sunil S.

In reply to sunils:

This means there is neither a req created nor a rsp. Which might be a consequence of the non-existing req.

In reply to sunils:

This isn’t an error. A sequence defines the variables ‘req’ and ‘rsp’ of the type that the sequence was typed with. It looks like you didn’t use these variables, so they are null.

In reply to cgales:

Hello Cgales,

From the above simulation view, when test start running, it only print that(only one name type size and value) and collect to extract phase.

I am doubting why it is not able to proceed further. Please suggest some possible reasons.

Thanks and Regards
Sunil S.

In reply to sunils:

Hi sunil did you implement the objection mechanism? It looks like there is no objection raised.