Simulation Hangs undefinitely

After printing uvm_topology simulation is getting hanged forever not proceeding to the next iteration.

[SIMULATION RESULT]

# //  Questa Sim
# //  Version 2022.1 linux Jan 29 2022
# //
# //  Copyright 1991-2022 Mentor Graphics Corporation
# //  All Rights Reserved.
# //
# //  QuestaSim and its associated documentation contain trade
# //  secrets and commercial or financial information that are the property of
# //  Mentor Graphics Corporation and are privileged, confidential,
# //  and exempt from disclosure under the Freedom of Information Act,
# //  5 U.S.C. Section 552. Furthermore, this information
# //  is prohibited from disclosure under the Trade Secrets Act,
# //  18 U.S.C. Section 1905.
# //

# Loading sv_std.std
# Loading work.wb_if(fast)
# Loading mtiUvm.uvm_pkg(fast)
# Loading work.uart_test_pkg(fast)
# Loading mtiUvm.questa_uvm_pkg(fast)
# Loading work.top(fast)
# Loading work.wb_if(fast__2)
# Loading work.uart_top(fast)
# Loading work.uart_wb(fast)
# Loading work.uart_regs(fast)
# Loading work.uart_transmitter(fast)
# Loading work.uart_tfifo(fast)
# Loading work.raminfr(fast)
# Loading work.uart_sync_flops(fast)
# Loading work.uart_receiver(fast)
# Loading work.uart_rfifo(fast)
# Loading /home/cad/eda/Questa-sim/questasim/uvm-1.1d/linux/uvm_dpi.so
# ** Warning: (vsim-PLI-3003) [TOFD] - System task or function '$formatf' is not                                                                               defined.
#    Time: 0 ps  Iteration: 0  Region: /uart_test_pkg::uart_xtn::do_print/#anonb                                                                              lk#119652807#57#2# File: ../wb_agt/uart_xtn.sv Line: 58
# ** Warning: (vsim-8634) Code was not compiled with coverage options.
# Sv_Seed = 211458694
#  log -r /*
# Unable to lock WLF file "wave_file1.wlf". Retrying 1 times, errno 11
# Unable to lock WLF file "wave_file1.wlf". Retrying 2 times, errno 11
# Unable to lock WLF file "wave_file1.wlf". Retrying 3 times, errno 11
# Cannot lock WLF file: "wave_file1.wlf"
#           errno 11: Resource temporarily unavailable.
# ** Warning: (vsim-WLF-5000) WLF file currently in use: wave_file1.wlf
#           File in use by: Vignesh  Hostname: mavenserver-RH2  ProcessID: 35960                                                                              19
#           Attempting to use alternate WLF file "./wlftaeune8".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: wave_file1.wlf
#           Using alternate file: ./wlftaeune8
# coverage save -onexit mem_cov1
# run -all
# ----------------------------------------------------------------
# UVM-1.1d
# (C) 2007-2013 Mentor Graphics Corporation
# (C) 2007-2013 Cadence Design Systems, Inc.
# (C) 2006-2013 Synopsys, Inc.
# (C) 2011-2013 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
#
#   ***********       IMPORTANT RELEASE NOTES         ************
#
#   You are using a version of the UVM library that has been compiled
#   with `UVM_NO_DEPRECATED undefined.
#   See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
#   You are using a version of the UVM library that has been compiled
#   with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
#   See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
#       (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: report                                                                              er [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: report                                                                              er [Questa UVM]  questa_uvm::init(+struct)
# (top.DUV1) UART INFO: Data bus width is 8. No Debug interface.
#
# (top.DUV1) UART INFO: Has baudrate output
#
# (top.DUV2) UART INFO: Data bus width is 8. No Debug interface.
#
# (top.DUV2) UART INFO: Has baudrate output
#
# UVM_INFO @ 0: reporter [RNTST] Running test TC1...
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# ----------------------------------------------------------------
# Name                         Type                    Size  Value
# ----------------------------------------------------------------
# uvm_test_top                 TC1                     -     @475
#   envh                       uart_env                -     @491
#     agt_top                  uart_agt_top            -     @499
#       uart_agt[0]            uart_agt                -     @616
#         drvh                 uart_driver             -     @761
#           rsp_port           uvm_analysis_port       -     @776
#           seq_item_port      uvm_seq_item_pull_port  -     @768
#         monh                 uart_monitor            -     @637
#           monitor_port       uvm_analysis_port       -     @644
#         sqrh                 uart_sequencer          -     @652
#           rsp_export         uvm_analysis_export     -     @659
#           seq_item_export    uvm_seq_item_pull_imp   -     @753
#           arbitration_queue  array                   0     -
#           lock_queue         array                   0     -
#           num_last_reqs      integral                32    'd1
#           num_last_rsps      integral                32    'd1
#       uart_agt[1]            uart_agt                -     @627
#         drvh                 uart_driver             -     @917
#           rsp_port           uvm_analysis_port       -     @932
#           seq_item_port      uvm_seq_item_pull_port  -     @924
#         monh                 uart_monitor            -     @793
#           monitor_port       uvm_analysis_port       -     @800
#         sqrh                 uart_sequencer          -     @808
#           rsp_export         uvm_analysis_export     -     @815
#           seq_item_export    uvm_seq_item_pull_imp   -     @909
#           arbitration_queue  array                   0     -
#           lock_queue         array                   0     -
#           num_last_reqs      integral                32    'd1
#           num_last_rsps      integral                32    'd1
#     vsqrh                    virtual_sequencer       -     @506
#       rsp_export             uvm_analysis_export     -     @513
#       seq_item_export        uvm_seq_item_pull_imp   -     @607
#       arbitration_queue      array                   0     -
#       lock_queue             array                   0     -
#       num_last_reqs          integral                32    'd1
#       num_last_rsps          integral                32    'd1
# ----------------------------------------------------------------
#....Here it is  not proceeding to next iteration

Also, included Driver and Monitor Files

class uart_driver extends uvm_driver#(uart_xtn);

        `uvm_component_utils(uart_driver)

        wb_agt_config cfg;

        virtual wb_if.WB_DRIV vif;

        extern  function new(string name="uart_driver",uvm_component parent);

        extern  function void build_phase(uvm_phase phase);

        extern function void connect_phase(uvm_phase phase);


        extern task run_phase(uvm_phase phase);

        extern task drive_item(uart_xtn xtn);

endclass


        function uart_driver::new(string name="uart_driver",uvm_component parent);
                super.new(name,parent);
        endfunction

        function void uart_driver::build_phase(uvm_phase phase);

                if(!uvm_config_db#(wb_agt_config)::get(this,"","wb_agt_config",cfg))
                        `uvm_fatal("AGT_CONFIG","Cannot get() env_cfg from config database. Have you set() it")

                super.build_phase(phase);
        endfunction

        function void uart_driver::connect_phase(uvm_phase phase);
                vif=cfg.vif;
        endfunction

        task uart_driver::run_phase(uvm_phase phase);

                vif.wb_driv.wb_rst_i<=1;
                        repeat(2) @(vif.wb_driv);
                vif.wb_driv.wb_rst_i<=0;
                forever
                        begin

                                seq_item_port.get_next_item(req);

                                drive_item(req);

                                seq_item_port.item_done();

                        end
        endtask

        task uart_driver::drive_item(uart_xtn xtn);
                @(vif.wb_driv);
                        vif.wb_driv.wb_dat_i<=xtn.wb_dat_i;
                        vif.wb_driv.wb_addr_i<=xtn.wb_addr_i;
                        vif.wb_driv.wb_we_i<=xtn.wb_we_i;

                xtn.wb_stb_i<=1'b1;
                xtn.wb_cyc_i<=1'b1;
                xtn.wb_sel_i<=4'b0001;
                @(vif.wb_driv);

                wait(xtn.wb_ack_o);
                        xtn.wb_cyc_i<=1'b0;
                        xtn.wb_stb_i<=1'b0;
                if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 0)
                        begin

                                wait(vif.wb_driv.wb_int_o)
                                        @(vif.wb_driv);
                                                xtn.wb_dat_o <= vif.wb_driv.wb_dat_o;
                                                seq_item_port.put_response(xtn);
                        end


        endtask



Monitor_file


class uart_monitor extends uvm_monitor;

        `uvm_component_utils(uart_monitor)

        virtual wb_if.WB_MON vif;

        wb_agt_config agt_cfg;

        uart_xtn xtn;

        uvm_analysis_port#(uart_xtn) monitor_port;

        function new(string name="uart_monitor",uvm_component parent);

                super.new(name,parent);

                monitor_port=new("monitor_port",this);
        endfunction

        function void build_phase(uvm_phase phase);
                super.build_phase(phase);

                if(!uvm_config_db#(wb_agt_config)::get(this,"","wb_agt_config",agt_cfg))
                `uvm_fatal("AGT_CONFIG","Cannot get() agt_cfg from config database. Have you set() it?")
        endfunction

        function void connect_phase(uvm_phase phase);

                        vif=agt_cfg.vif;
        endfunction



        task run_phase(uvm_phase phase);

                forever
                        collect_data();
        endtask

        task collect_data();

                xtn=uart_xtn::type_id::create("xtn");
                wait(vif.wb_mon.wb_ack_o);
                
                @(vif.wb_mon);
                        xtn.wb_addr_i   <= vif.wb_mon.wb_addr_i;
                        xtn.wb_we_i     <= vif.wb_mon.wb_we_i;

                        if(xtn.wb_addr_i == 3 && xtn.wb_we_i == 1)

                                        xtn.lcr <= vif.wb_mon.wb_dat_i;
                        if(xtn.wb_addr_i == 1  && xtn.wb_we_i == 1 && xtn.lcr[7] ==1)
                                        xtn.dlr_1  <= vif.wb_mon.wb_dat_i;

                        if(xtn.wb_addr_i == 0  && xtn.wb_we_i ==1 && xtn.lcr[7]==1)
                                        xtn.dlr_2  <= vif.wb_mon.wb_dat_i;

                        if(xtn.wb_addr_i == 0 && xtn.wb_we_i == 0 && xtn.lcr[7] == 0)
                                        xtn.rb.push_back(vif.wb_mon.wb_dat_i);




                        if(xtn.wb_addr_i == 0 && xtn.wb_we_i == 1 && xtn.lcr[7] == 0)
                                        xtn.thr.push_back(vif.wb_mon.wb_dat_i);
                        if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 1)
                                        xtn.fcr <= vif.wb_mon.wb_dat_i;
                        if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 0)
                                        begin
                                                wait(vif.wb_mon.wb_int_o)
                                                        xtn.iir <= vif.wb_mon.wb_dat_o;

                                        end
        endtask


endclass


In reply to Vignesh_18:

Unfortunately, that’s not enough information to help you. What were you expecting to be printed out next? What happens if you take away the code that prints the topology?

Also, I would check through your compilation logs for any warning that can’t be explained. The warning about $formatf is a typos that probably should have been $sformatf.

There are tool debugging capabilities to help you step through your code to find you exactly where it is hanging.

Thank you so much for your response. Actually, I am a newbie to UVM. Here if i tried not to print topology like the simulation log would be:
run -all

----------------------------------------------------------------

UVM-1.1d

(C) 2007-2013 Mentor Graphics Corporation

(C) 2007-2013 Cadence Design Systems, Inc.

(C) 2006-2013 Synopsys, Inc.

(C) 2011-2013 Cypress Semiconductor Corp.

----------------------------------------------------------------

*********** IMPORTANT RELEASE NOTES ************

You are using a version of the UVM library that has been compiled

with `UVM_NO_DEPRECATED undefined.

See 404 for more details.

You are using a version of the UVM library that has been compiled

with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.

See 404 for more details.

(Specify +UVM_NO_RELNOTES to turn off this notice)

UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: reporter [Questa UVM] QUESTA_UVM-1.2.3

UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: reporter [Questa UVM] questa_uvm::init(+struct)

(top.DUV1) UART INFO: Data bus width is 8. No Debug interface.

(top.DUV1) UART INFO: Has baudrate output

(top.DUV2) UART INFO: Data bus width is 8. No Debug interface.

(top.DUV2) UART INFO: Has baudrate output

UVM_INFO @ 0: reporter [RNTST] Running test TC1…

And after adding some debug statements in the driver and monitor I had found that I am not getting an ack signal and I suspect that wait statements might be an issue I guess.

Here is the simulation log after including debug statements

UVM_INFO @ 0: reporter [RNTST] Running test TC1…

UVM_INFO …/wb_agt/uart_driver.sv(67) @ 35000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [Debug] waiting for ack

Could you help me with how I have to proceed further I am attaching all files
below:
DRIVER CODE

class uart_driver extends uvm_driver#(uart_xtn);

        `uvm_component_utils(uart_driver)

        wb_agt_config cfg;

        virtual wb_if.WB_DRIV vif;

        extern  function new(string name="uart_driver",uvm_component parent);

        extern  function void build_phase(uvm_phase phase);

        extern function void connect_phase(uvm_phase phase);


        extern task run_phase(uvm_phase phase);

        extern task drive_item(uart_xtn xtn);

endclass


        function uart_driver::new(string name="uart_driver",uvm_component parent);
                super.new(name,parent);
        endfunction

        function void uart_driver::build_phase(uvm_phase phase);

                if(!uvm_config_db#(wb_agt_config)::get(this,"","wb_agt_config",cfg))
                        `uvm_fatal("AGT_CONFIG","Cannot get() env_cfg from config database. Have you set() it")

                super.build_phase(phase);
        endfunction

        function void uart_driver::connect_phase(uvm_phase phase);
                vif=cfg.vif;
        endfunction

        task uart_driver::run_phase(uvm_phase phase);

                vif.wb_driv.wb_rst_i<=1;
                        repeat(2) @(vif.wb_driv);
                vif.wb_driv.wb_rst_i<=0;
                
                forever
                        begin
                                #5;
                                seq_item_port.get_next_item(req);

                                drive_item(req);

                                seq_item_port.item_done();

                        end
        endtask

        task uart_driver::drive_item(uart_xtn xtn);
                @(vif.wb_driv);
                        vif.wb_driv.wb_dat_i<=xtn.wb_dat_i;
                        vif.wb_driv.wb_addr_i<=xtn.wb_addr_i;
                        vif.wb_driv.wb_we_i<=xtn.wb_we_i;
                @(vif.wb_driv);
                xtn.wb_stb_i<=1'b1;
                xtn.wb_cyc_i<=1'b1;
                xtn.wb_sel_i<=4'b0001;
                //@(vif.wb_driv);
                `uvm_info("Debug","waiting for ack",UVM_LOW)
                wait(xtn.wb_ack_o);
                        @(vif.wb_driv);
                        xtn.wb_cyc_i<=1'b0;
                        xtn.wb_stb_i<=1'b0;
                if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 0)
                        begin
                                `uvm_info("Debug","waiting for int_o signal",UVM_LOW)
                                wait(vif.wb_driv.wb_int_o)
                                        @(vif.wb_driv);
                                                xtn.wb_dat_o <= vif.wb_driv.wb_dat_o;
                                                seq_item_port.put_response(xtn);
                         end
endclass                                                                 


                                                   

MONITOR

class uart_monitor extends uvm_monitor;

        `uvm_component_utils(uart_monitor)

        virtual wb_if.WB_MON vif;

        wb_agt_config agt_cfg;

        uart_xtn xtn;

        uvm_analysis_port#(uart_xtn) monitor_port;

        function new(string name="uart_monitor",uvm_component parent);

                super.new(name,parent);

                monitor_port=new("monitor_port",this);
        endfunction

        function void build_phase(uvm_phase phase);
                super.build_phase(phase);

                if(!uvm_config_db#(wb_agt_config)::get(this,"","wb_agt_config",agt_cfg))
                `uvm_fatal("AGT_CONFIG","Cannot get() agt_cfg from config database. Have you set() it?")
        endfunction

        function void connect_phase(uvm_phase phase);

                        vif=agt_cfg.vif;
        endfunction



        task run_phase(uvm_phase phase);

                forever

                        #10;

                        collect_data();
        endtask

        task collect_data();
                  task collect_data();

                xtn=uart_xtn::type_id::create("xtn");
                `uvm_info("Debug","Waiting for ack",UVM_LOW);
                wait(vif.wb_mon.wb_ack_o);

                @(vif.wb_mon);
                        xtn.wb_addr_i   <= vif.wb_mon.wb_addr_i;
                        xtn.wb_we_i     <= vif.wb_mon.wb_we_i;

                        if(xtn.wb_addr_i == 3 && xtn.wb_we_i == 1)

                                        xtn.lcr <= vif.wb_mon.wb_dat_i;
                        if(xtn.wb_addr_i == 1  && xtn.wb_we_i == 1 && xtn.lcr[7] ==1)
                                        xtn.dlr_1  <= vif.wb_mon.wb_dat_i;

                        if(xtn.wb_addr_i == 0  && xtn.wb_we_i ==1 && xtn.lcr[7]==1)
                                        xtn.dlr_2  <= vif.wb_mon.wb_dat_i;

                        if(xtn.wb_addr_i == 0 && xtn.wb_we_i == 0 && xtn.lcr[7] == 0)
                                        xtn.rb.push_back(vif.wb_mon.wb_dat_i);




                        if(xtn.wb_addr_i == 0 && xtn.wb_we_i == 1 && xtn.lcr[7] == 0)
                                        xtn.thr.push_back(vif.wb_mon.wb_dat_i);
                        if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 1)
                                        xtn.fcr <= vif.wb_mon.wb_dat_i;
                        if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 0)
                                        begin
                                                wait(vif.wb_mon.wb_int_o)
                                                        xtn.iir <= vif.wb_mon.wb_dat_o;

                                        end
        endtask


endclass

TEST FILE


class uart_base_test extends uvm_test;

        `uvm_component_utils(uart_base_test)

        uart_env envh;
        uart_env_config env_config;

        wb_agt_config agt_config[];

        int no_of_duts = 2;

        int no_of_agts = 2;

        int  has_wb_agent=1;




//      int has_virtual_inf=2;

        extern function new(string name="uart_base_test",uvm_component parent);

        extern function void  build_phase(uvm_phase phase);

        extern function void  config_uart();

//      extern function void end_of_elaboration_phase(uvm_phase phase);


endclass

function uart_base_test::new(string name="uart_base_test",uvm_component parent);

                super.new(name,parent);
endfunction

function void  uart_base_test::config_uart();
                  if(has_wb_agent)
                        begin

                                agt_config=new[no_of_duts];
                        foreach(agt_config[i])
                                begin

                                        agt_config[i]=wb_agt_config::type_id::create($sformatf("agt_config[%0d]",i));

                                        if(!uvm_config_db#(virtual wb_if)::get(this," ",$sformatf("vif_%0d",i),agt_config[i].vif))

                                                `uvm_fatal("VIF_CONFIG","Cannot get() interface vif from uvm_config_db. Have you set() it?")

                                        agt_config[i].is_active = UVM_ACTIVE;

                                        env_config.agt_config[i]=agt_config[i];

                                end

                        end

                        env_config.no_of_agts=no_of_agts;
                        env_config.no_of_duts=no_of_duts;
                        env_config.has_wb_agent= has_wb_agent;


endfunction


function void uart_base_test::build_phase(uvm_phase phase);

                env_config=uart_env_config::type_id::create("env_config");

                if(has_wb_agent)

                        env_config.agt_config=new[no_of_duts];

 config_uart;

                uvm_config_db#(uart_env_config)::set(this,"*","uart_env_config",env_config);

                super.build_phase(phase);

        //ENVIRONMENT CREATION//
                envh=uart_env::type_id::create("envh",this);


endfunction

/*function void  uart_base_test::end_of_elaboration_phase(uvm_phase phase);
                uvm_top.print_topology();
endfunction*/


class TC1 extends uart_base_test;
                `uvm_component_utils(TC1)

                v_seq1 vs1;




        function new(string name="TC1",uvm_component parent);
                        super.new(name,parent);
        endfunction

        function void build_phase(uvm_phase phase);
                                                            function void build_phase(uvm_phase phase);
                        super.build_phase(phase);

        endfunction

        task run_phase(uvm_phase phase);
                phase.raise_objection(this);
                vs1=v_seq1::type_id::create("vs1");
                vs1.start(envh.vsqrh);
                phase.drop_objection(this);

        endtask

endclass

               
   

In reply to Vignesh_18:
Looks like your ack does not appear. Because this is the last message in your log-file.
Please check your DUT wrt to the ack.

Okay, thanks so much chr_sue

In reply to chr_sue:

In reply to Vignesh_18:
Looks like your ack does not appear. Because this is the last message in your log-file.
Please check your DUT wrt to the ack.

Tried looking for DUT and everything works fine. But still, this issue is persisting

In reply to Vignesh_18:
Does your clock signal appear in the driver/monitor. You do not see this in the waveforms. But you can insert prior and after the clock event a diagnostic message for debug use.

In reply to chr_sue:

Like should we attach clk signal before and after the clk event? Does what it means?

In reply to Vignesh_18:

No you should do something like this:

`uvm_info(get_type_name(), "before clk event", UVM_MEDIUM)
@(vif.wb_mon);
`uvm_info(get_type_name(), "after clk event", UVM_MEDIUM)

In reply to chr_sue:

In reply to Vignesh_18:
No you should do something like this:

`uvm_info(get_type_name(), "before clk event", UVM_MEDIUM)
@(vif.wb_mon);
`uvm_info(get_type_name(), "after clk event", UVM_MEDIUM)

Okay will try…Thanks

In reply to chr_sue:

In reply to Vignesh_18:
No you should do something like this:

`uvm_info(get_type_name(), "before clk event", UVM_MEDIUM)
@(vif.wb_mon);
`uvm_info(get_type_name(), "after clk event", UVM_MEDIUM)

UVM_INFO @ 0: reporter [RNTST] Running test TC1…

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 20000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 25000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 25000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 35000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 35000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 35000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 45000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 50000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 55000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 55000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 65000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 65000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 65000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 75000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 80000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 85000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 85000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 95000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 95000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 95000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 105000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 110000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 115000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 115000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 125000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 125000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 125000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 135000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 140000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 145000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 145000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 155000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 155000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 155000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 165000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 170000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 175000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 175000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 185000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 185000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 185000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 195000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 200000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 205000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 205000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 215000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 215000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 215000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 225000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 230000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 235000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 235000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 245000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 245000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 245000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 255000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(81) @ 255000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [Debug] waiting for int_o signal

UVM_INFO …/wb_agt/uart_driver.sv(83) @ 255000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] Before clk event

UVM_INFO …/wb_agt/uart_driver.sv(85) @ 265000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 265000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 270000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 270000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 290000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 290000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 290000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 310000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 315000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 330000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 330000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 350000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 350000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 350000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 370000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 375000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 390000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 390000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 410000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 410000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 410000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 430000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 435000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 450000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 450000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 470000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 470000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 470000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 490000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 495000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 510000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 510000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 530000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 530000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 530000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 550000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 555000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 570000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 570000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 590000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 590000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 590000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 610000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 615000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 630000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 630000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 650000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 650000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 650000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 670000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 675000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 690000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 690000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 710000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 710000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [Debug] waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(73) @ 710000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(76) @ 730000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(81) @ 730000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [Debug] waiting for int_o signal

UVM_INFO …/wb_agt/uart_driver.sv(83) @ 730000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] Before clk event

UVM_INFO …/wb_agt/uart_driver.sv(85) @ 750000: uvm_test_top.envh.agt_top.uart_agt[1].drvh [uart_driver] after clk event

UVM_INFO verilog_src/uvm-1.1d/src/base/uvm_objection.svh(1267) @ 750000: reporter [TEST_DONE] ‘run’ phase is ready to proceed to the ‘extract’ phase

After adding messages between each and every clk event it seems that clk is working fine and after commenting wait statements i am getting all my clk events executed properly…i assume that ACK is not received properly…Could you please help me with this??

In reply to Vignesh_18:

You see your driver works properly with respect to the synchronization.
You can now do the same in the monitor. But my guess is the monitor stops because of the ack, which does not appear. To investigate this you have to look to your DUT and find out why the ack doesn’t get asserted.

In reply to chr_sue:

In reply to Vignesh_18:
You see your driver works properly with respect to the synchronization.
You can now do the same in the monitor. But my guess is the monitor stops because of the ack, which does not appear. To investigate this you have to look to your DUT and find out why the ack doesn’t get asserted.

UVM_INFO @ 0: reporter [RNTST] Running test TC1…

UVM_INFO …/wb_agt/uart_monitor.sv(46) @ 0: uvm_test_top.envh.agt_top.uart_agt[1].monh [Debug] Waiting for ack

UVM_INFO …/wb_agt/uart_monitor.sv(46) @ 0: uvm_test_top.envh.agt_top.uart_agt[0].monh [Debug] Waiting for ack

UVM_INFO …/wb_agt/uart_driver.sv(58) @ 15000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(60) @ 25000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(64) @ 25000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] before clk event

UVM_INFO …/wb_agt/uart_driver.sv(66) @ 35000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [uart_driver] after clk event

UVM_INFO …/wb_agt/uart_driver.sv(71) @ 35000: uvm_test_top.envh.agt_top.uart_agt[0].drvh [Debug] waiting for ack

Break key hit

This is the simulation log after including all the debug messages in both driver/monitor and it shows the monitor waiting for ack prematurely… are there any codes that I needed to share for clarity also DUT is absolutely fine…Don’t know why it is not working properly…Thank you so much chr_sue and really helped me how to debug a piece of code

In reply to Vignesh_18:

Attached here all the files
Transaction file

class uart_xtn extends uvm_sequence_item;


        `uvm_object_utils(uart_xtn)

        rand logic [2:0] wb_addr_i;
        rand logic [7:0] wb_dat_i;
        rand logic wb_we_i;

        bit  wb_stb_i;
        bit  wb_cyc_i;
        bit  wb_ack_o;

        bit  [3:0]wb_sel_i;
        bit  [7:0]wb_dat_o;

        //REGISTERS LIST

        bit [7:0] thr[$];
        bit [7:0] rb[$];
        bit [7:0] ier;
        bit [7:0] iir;
        bit [7:0] fcr;
        bit [7:0] lcr;
        bit [7:0] lsr;
        bit [7:0] dlr_1;
        bit [7:0] dlr_2;






        extern function new(string name="uart_xtn");
        extern function void do_print(uvm_printer printer);

endclass

function uart_xtn::new(string name="uart_xtn");
        super.new(name);
endfunction

function void uart_xtn::do_print(uvm_printer printer);

   super.do_print(printer);

        printer.print_field("Wishbone Addr", this.wb_addr_i,3,UVM_DEC);

        printer.print_field("Wishbone Data",this.wb_dat_i,8,UVM_BIN);

        printer.print_field("Wishbone Write",this.wb_we_i,1,UVM_DEC);

        //REGISTER PRINTING//

        foreach(thr[i])
                printer.print_field($sformatf("THR[%0d]",i),this.thr[i],8,UVM_BIN);
        foreach(rb[i])
                printer.print_field($sformatf("RB[%0d]",i),this.rb[i],8,UVM_BIN);
        printer.print_field("IER",this.ier,8,UVM_BIN);
        printer.print_field("IIR",this.iir,8,UVM_BIN);
        printer.print_field("FCR",this.fcr,8,UVM_BIN);
        printer.print_field("LCR",this.lcr,8,UVM_BIN);
        printer.print_field("LSR",this.lsr,8,UVM_BIN);
        printer.print_field("DLR_1",this.dlr_1,8,UVM_BIN);
        printer.print_field("DLR_2",this.dlr_2,8,UVM_BIN);


endfunction

**Driver File**

``` verilog
class uart_driver extends uvm_driver#(uart_xtn);

        `uvm_component_utils(uart_driver)

        wb_agt_config cfg;

        virtual wb_if.WB_DRIV vif;

        extern  function new(string name="uart_driver",uvm_component parent);

        extern  function void build_phase(uvm_phase phase);

        extern function void connect_phase(uvm_phase phase);


        extern task run_phase(uvm_phase phase);

        extern task drive_item(uart_xtn xtn);

endclass


        function uart_driver::new(string name="uart_driver",uvm_component parent);
                super.new(name,parent);
        endfunction

        function void uart_driver::build_phase(uvm_phase phase);

                if(!uvm_config_db#(wb_agt_config)::get(this,"","wb_agt_config",cfg))
                        `uvm_fatal("AGT_CONFIG","Cannot get() env_cfg from config database. Have you set() it")

                super.build_phase(phase);
        endfunction

        function void uart_driver::connect_phase(uvm_phase phase);
                vif=cfg.vif;
        endfunction

        task uart_driver::run_phase(uvm_phase phase);

                vif.wb_driv.wb_rst_i<=1;
                        repeat(2) @(vif.wb_driv);
                vif.wb_driv.wb_rst_i<=0;
forever
                        begin

                                seq_item_port.get_next_item(req);

                                drive_item(req);

                                seq_item_port.item_done();

                        end
        endtask

        task uart_driver::drive_item(uart_xtn xtn);
                `uvm_info(get_type_name(),"before clk event",UVM_MEDIUM)
                @(vif.wb_driv);
                `uvm_info(get_type_name(),"after clk event",UVM_MEDIUM)
                        vif.wb_driv.wb_dat_i<=xtn.wb_dat_i;
                        vif.wb_driv.wb_addr_i<=xtn.wb_addr_i;
                        vif.wb_driv.wb_we_i<=xtn.wb_we_i;
                `uvm_info(get_type_name(),"before clk event",UVM_MEDIUM)
                @(vif.wb_driv);
                `uvm_info(get_type_name(),"after clk event",UVM_MEDIUM)
                xtn.wb_stb_i<=1'b1;
                xtn.wb_cyc_i<=1'b1;
                xtn.wb_sel_i<=4'b0001;
                //@(vif.wb_driv);
                `uvm_info("Debug","waiting for ack",UVM_LOW)
                wait(xtn.wb_ack_o);
                        `uvm_info(get_type_name(),"before clk event",UVM_MEDIUM)

                        @(vif.wb_driv);
                        `uvm_info(get_type_name(),"after clk event",UVM_MEDIUM)
                        xtn.wb_cyc_i<=1'b0;
                        xtn.wb_stb_i<=1'b0;
                if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 0)
 begin
                                        `uvm_info("Debug","waiting for int_o signal",UVM_LOW)
                                        wait(vif.wb_driv.wb_int_o)
                                        `uvm_info(get_type_name(),"Before clk event",UVM_MEDIUM)
                                        @(vif.wb_driv);
                                        `uvm_info(get_type_name(),"after clk event",UVM_MEDIUM)
                                                xtn.wb_dat_o <= vif.wb_driv.wb_dat_o;
                                                seq_item_port.put_response(xtn);
                        end


        endtask



Monitor File

class uart_monitor extends uvm_monitor;

        `uvm_component_utils(uart_monitor)

        virtual wb_if.WB_MON vif;

        wb_agt_config agt_cfg;

        uart_xtn xtn;

        uvm_analysis_port#(uart_xtn) monitor_port;

        function new(string name="uart_monitor",uvm_component parent);

                super.new(name,parent);

                monitor_port=new("monitor_port",this);
        endfunction

        function void build_phase(uvm_phase phase);
                super.build_phase(phase);

                if(!uvm_config_db#(wb_agt_config)::get(this,"","wb_agt_config",agt_cfg))
                `uvm_fatal("AGT_CONFIG","Cannot get() agt_cfg from config database. Have you set() it?")
        endfunction

        function void connect_phase(uvm_phase phase);

                        vif=agt_cfg.vif;
        endfunction



        task run_phase(uvm_phase phase);

                forever



                        collect_data();
        endtask

        task collect_data();
                     task collect_data();

                xtn=uart_xtn::type_id::create("xtn");
                `uvm_info("Debug","Waiting for ack",UVM_LOW);
                wait(vif.wb_mon.wb_ack_o);
                `uvm_info(get_type_name(),"Before clk event",UVM_MEDIUM)
                @(vif.wb_mon);
                `uvm_info(get_type_name(),"After clk event",UVM_MEDIUM)
                        xtn.wb_addr_i   <= vif.wb_mon.wb_addr_i;
                        xtn.wb_we_i     <= vif.wb_mon.wb_we_i;

                        if(xtn.wb_addr_i == 3 && xtn.wb_we_i == 1)

                                        xtn.lcr <= vif.wb_mon.wb_dat_i;
                        if(xtn.wb_addr_i == 1  && xtn.wb_we_i == 1 && xtn.lcr[7] ==1)
                                        xtn.dlr_1  <= vif.wb_mon.wb_dat_i;

                        if(xtn.wb_addr_i == 0  && xtn.wb_we_i ==1 && xtn.lcr[7]==1)
                                        xtn.dlr_2  <= vif.wb_mon.wb_dat_i;

                        if(xtn.wb_addr_i == 0 && xtn.wb_we_i == 0 && xtn.lcr[7] == 0)
                                        xtn.rb.push_back(vif.wb_mon.wb_dat_i);




                        if(xtn.wb_addr_i == 0 && xtn.wb_we_i == 1 && xtn.lcr[7] == 0)
                                        xtn.thr.push_back(vif.wb_mon.wb_dat_i);
                        if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 1)
                                        xtn.fcr <= vif.wb_mon.wb_dat_i;
                        if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 0)
                                        begin
                                                wait(vif.wb_mon.wb_int_o)
                                                        xtn.iir <= vif.wb_mon.wb_dat_o;

                                        end
        endtask


endclass


Seqeunce File

class base_seq extends uvm_sequence#(uart_xtn);

        `uvm_object_utils(base_seq)

        function new(string name="base_seq");
                super.new(name);
        endfunction

endclass

class seq1 extends base_seq;

        `uvm_object_utils(seq1);

        function new(string name="seq1");
                        super.new(name);
        endfunction

        virtual task body();
                begin

                        req=uart_xtn::type_id::create("req");
                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b1000_0000;wb_we_i==1'b1;wb_addr_i==3;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0000_0000;wb_we_i==1'b1;wb_addr_i==1;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0011_0110;wb_we_i==1'b1;wb_addr_i==0;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0000_0011;wb_we_i==1'b1;wb_addr_i==3;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0000_0001;wb_we_i==1'b1;wb_addr_i==1;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0000_0110;wb_we_i==1'b1;wb_addr_i==2;})
                                    finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0000_0111;wb_we_i==1'b1;wb_addr_i==0;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_addr_i==2; wb_we_i==0;})
                        finish_item(req);

                        get_response(req);

                        if(req.wb_dat_o == 8'b0000_0110)
                                begin
                                        start_item(req);
                                        assert(req.randomize() with {wb_we_i==0;wb_addr_i==5;})
                                        finish_item(req);
                                end
                        if(req.wb_dat_o == 8'b0000_0100)
                                begin
                                        start_item(req);
                                        assert(req.randomize() with { wb_we_i == 0 ;wb_addr_i == 0 ;})
                                        finish_item(req);
                                end
                        if(req.wb_dat_o == 8'b0000_1100)
                                begin
                                        start_item(req);
                                        assert(req.randomize() with {wb_we_i == 0;wb_addr_i == 0;})
                                        finish_item(req);
                                end
                        if(req.wb_dat_o ==  8'b0000_0010)
                                begin
                                        start_item(req);
                                        assert(req.randomize() with { wb_we_i == 1;wb_addr_i == 0;wb_dat_i == 8'b0000_0111;})
                                        finish_item(req);
                                end

                end
        endtask
endclass

class seq2 extends base_seq;
       
                `uvm_object_utils(seq2)
                function new(string name="seq2");
                                super.new(name);
                endfunction

                virtual task body();
                begin

                        req=uart_xtn::type_id::create("req");
                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b1000_0000;wb_we_i==1'b1;wb_addr_i==3;})
                        finish_item(req);


                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0000_0000;wb_we_i==1'b1;wb_addr_i==1;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0001_1011;wb_we_i==1'b1;wb_addr_i==0;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0000_0011;wb_we_i==1'b1;wb_addr_i==3;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0000_0001;wb_we_i==1'b1;wb_addr_i==1;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0000_0110;wb_we_i==1'b1;wb_addr_i==2;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_dat_i==8'b0000_0111;wb_we_i==1'b1;wb_addr_i==0;})
                        finish_item(req);

                        start_item(req);
                        assert(req.randomize() with {wb_addr_i==2; wb_we_i==0;})
                        finish_item(req);

                        get_response(req);
if(req.wb_dat_o == 8'b0000_0110)
                                begin
                                        start_item(req);
                                assert(req.randomize() with     {wb_we_i==0;
                                        wb_addr_i==5;})
                                        finish_item(req);
                                end
                        if(req.wb_dat_o == 8'b0000_0100)
                                begin
                                        start_item(req);
                                assert(req.randomize() with {   wb_we_i ==0 ;
                                        wb_addr_i ==0 ;})
                                        finish_item(req);
                                end
                        if(req.wb_dat_o == 8'b0000_1100)
                                begin
                                        start_item(req);
                                        assert(req.randomize() with {wb_we_i == 0;
                                        wb_addr_i == 0;})
                                        finish_item(req);
                                end
                        if(req.wb_dat_o ==  8'b0000_0010)
                                begin
                                        start_item(req);
                                        assert(req.randomize() with {wb_we_i == 1;
                                        wb_addr_i == 0;
                                        wb_dat_i == 8'b0000_0111;})
                                        finish_item(req);
                                end
    end
        endtask
endclass



                       

TEST FILE

class uart_base_test extends uvm_test;
 
        `uvm_component_utils(uart_base_test)
 
        uart_env envh;
        uart_env_config env_config;
 
        wb_agt_config agt_config[];
 
        int no_of_duts = 2;
 
        int no_of_agts = 2;
 
        int  has_wb_agent=1;
 
 
 
 
//      int has_virtual_inf=2;
 
        extern function new(string name="uart_base_test",uvm_component parent);
 
        extern function void  build_phase(uvm_phase phase);
 
        extern function void  config_uart();
 
//      extern function void end_of_elaboration_phase(uvm_phase phase);
 
 
endclass
 
function uart_base_test::new(string name="uart_base_test",uvm_component parent);
 
                super.new(name,parent);
endfunction
 
function void  uart_base_test::config_uart();
                  if(has_wb_agent)
                        begin
 
                                agt_config=new[no_of_duts];
                        foreach(agt_config[i])
                                begin
 
                                        agt_config[i]=wb_agt_config::type_id::create($sformatf("agt_config[%0d]",i));
 
                                        if(!uvm_config_db#(virtual wb_if)::get(this," ",$sformatf("vif_%0d",i),agt_config[i].vif))
 
                                                `uvm_fatal("VIF_CONFIG","Cannot get() interface vif from uvm_config_db. Have you set() it?")
 
                                        agt_config[i].is_active = UVM_ACTIVE;
 
                                        env_config.agt_config[i]=agt_config[i];
 
                                end
 
                        end
 
                        env_config.no_of_agts=no_of_agts;
                        env_config.no_of_duts=no_of_duts;
                        env_config.has_wb_agent= has_wb_agent;
 
 
endfunction
 
 
function void uart_base_test::build_phase(uvm_phase phase);
 
                env_config=uart_env_config::type_id::create("env_config");
 
                if(has_wb_agent)
 
                        env_config.agt_config=new[no_of_duts];
 
 config_uart;
 
                uvm_config_db#(uart_env_config)::set(this,"*","uart_env_config",env_config);
 
                super.build_phase(phase);
 
        //ENVIRONMENT CREATION//
                envh=uart_env::type_id::create("envh",this);
 
 
endfunction
 
/*function void  uart_base_test::end_of_elaboration_phase(uvm_phase phase);
                uvm_top.print_topology();
endfunction*/
 
 
class TC1 extends uart_base_test;
                `uvm_component_utils(TC1)
 
                v_seq1 vs1;
 
 
 
 
        function new(string name="TC1",uvm_component parent);
                        super.new(name,parent);
        endfunction
 
        function void build_phase(uvm_phase phase);
                                                            function void build_phase(uvm_phase phase);
                        super.build_phase(phase);
 
        endfunction
 
        task run_phase(uvm_phase phase);
                phase.raise_objection(this);
                vs1=v_seq1::type_id::create("vs1");
                vs1.start(envh.vsqrh);
                phase.drop_objection(this);
 
        endtask
 
endclass
 
 
 

In reply to Vignesh_18:

The ack signal comes from the RTL. Do you have a DUT instntiated in the toplevel module?
Please double check.

In reply to chr_sue:

In reply to Vignesh_18:
The ack signal comes from the RTL. Do you have a DUT instntiated in the toplevel module?
Please double check.

Thank you so much for your response chr_sue. Actually, I rechecked once using waveform and found that ack signal is not appearing so i rechecked driver logic once and found that

wait(xtn.wb_ack_o);

…Inside the wait statement i have wrote xtn.wb_ack_0 instead i should have written

wait(vif.wb_driv.wb_ack_o)