After printing uvm_topology simulation is getting hanged forever not proceeding to the next iteration.
[SIMULATION RESULT]
# // Questa Sim
# // Version 2022.1 linux Jan 29 2022
# //
# // Copyright 1991-2022 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // QuestaSim and its associated documentation contain trade
# // secrets and commercial or financial information that are the property of
# // Mentor Graphics Corporation and are privileged, confidential,
# // and exempt from disclosure under the Freedom of Information Act,
# // 5 U.S.C. Section 552. Furthermore, this information
# // is prohibited from disclosure under the Trade Secrets Act,
# // 18 U.S.C. Section 1905.
# //
# Loading sv_std.std
# Loading work.wb_if(fast)
# Loading mtiUvm.uvm_pkg(fast)
# Loading work.uart_test_pkg(fast)
# Loading mtiUvm.questa_uvm_pkg(fast)
# Loading work.top(fast)
# Loading work.wb_if(fast__2)
# Loading work.uart_top(fast)
# Loading work.uart_wb(fast)
# Loading work.uart_regs(fast)
# Loading work.uart_transmitter(fast)
# Loading work.uart_tfifo(fast)
# Loading work.raminfr(fast)
# Loading work.uart_sync_flops(fast)
# Loading work.uart_receiver(fast)
# Loading work.uart_rfifo(fast)
# Loading /home/cad/eda/Questa-sim/questasim/uvm-1.1d/linux/uvm_dpi.so
# ** Warning: (vsim-PLI-3003) [TOFD] - System task or function '$formatf' is not defined.
# Time: 0 ps Iteration: 0 Region: /uart_test_pkg::uart_xtn::do_print/#anonb lk#119652807#57#2# File: ../wb_agt/uart_xtn.sv Line: 58
# ** Warning: (vsim-8634) Code was not compiled with coverage options.
# Sv_Seed = 211458694
# log -r /*
# Unable to lock WLF file "wave_file1.wlf". Retrying 1 times, errno 11
# Unable to lock WLF file "wave_file1.wlf". Retrying 2 times, errno 11
# Unable to lock WLF file "wave_file1.wlf". Retrying 3 times, errno 11
# Cannot lock WLF file: "wave_file1.wlf"
# errno 11: Resource temporarily unavailable.
# ** Warning: (vsim-WLF-5000) WLF file currently in use: wave_file1.wlf
# File in use by: Vignesh Hostname: mavenserver-RH2 ProcessID: 35960 19
# Attempting to use alternate WLF file "./wlftaeune8".
# ** Warning: (vsim-WLF-5001) Could not open WLF file: wave_file1.wlf
# Using alternate file: ./wlftaeune8
# coverage save -onexit mem_cov1
# run -all
# ----------------------------------------------------------------
# UVM-1.1d
# (C) 2007-2013 Mentor Graphics Corporation
# (C) 2007-2013 Cadence Design Systems, Inc.
# (C) 2006-2013 Synopsys, Inc.
# (C) 2011-2013 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
#
# *********** IMPORTANT RELEASE NOTES ************
#
# You are using a version of the UVM library that has been compiled
# with `UVM_NO_DEPRECATED undefined.
# See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
# You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(277) @ 0: report er [Questa UVM] QUESTA_UVM-1.2.3
# UVM_INFO verilog_src/questa_uvm_pkg-1.2/src/questa_uvm_pkg.sv(278) @ 0: report er [Questa UVM] questa_uvm::init(+struct)
# (top.DUV1) UART INFO: Data bus width is 8. No Debug interface.
#
# (top.DUV1) UART INFO: Has baudrate output
#
# (top.DUV2) UART INFO: Data bus width is 8. No Debug interface.
#
# (top.DUV2) UART INFO: Has baudrate output
#
# UVM_INFO @ 0: reporter [RNTST] Running test TC1...
# UVM_INFO @ 0: reporter [UVMTOP] UVM testbench topology:
# ----------------------------------------------------------------
# Name Type Size Value
# ----------------------------------------------------------------
# uvm_test_top TC1 - @475
# envh uart_env - @491
# agt_top uart_agt_top - @499
# uart_agt[0] uart_agt - @616
# drvh uart_driver - @761
# rsp_port uvm_analysis_port - @776
# seq_item_port uvm_seq_item_pull_port - @768
# monh uart_monitor - @637
# monitor_port uvm_analysis_port - @644
# sqrh uart_sequencer - @652
# rsp_export uvm_analysis_export - @659
# seq_item_export uvm_seq_item_pull_imp - @753
# arbitration_queue array 0 -
# lock_queue array 0 -
# num_last_reqs integral 32 'd1
# num_last_rsps integral 32 'd1
# uart_agt[1] uart_agt - @627
# drvh uart_driver - @917
# rsp_port uvm_analysis_port - @932
# seq_item_port uvm_seq_item_pull_port - @924
# monh uart_monitor - @793
# monitor_port uvm_analysis_port - @800
# sqrh uart_sequencer - @808
# rsp_export uvm_analysis_export - @815
# seq_item_export uvm_seq_item_pull_imp - @909
# arbitration_queue array 0 -
# lock_queue array 0 -
# num_last_reqs integral 32 'd1
# num_last_rsps integral 32 'd1
# vsqrh virtual_sequencer - @506
# rsp_export uvm_analysis_export - @513
# seq_item_export uvm_seq_item_pull_imp - @607
# arbitration_queue array 0 -
# lock_queue array 0 -
# num_last_reqs integral 32 'd1
# num_last_rsps integral 32 'd1
# ----------------------------------------------------------------
#....Here it is not proceeding to next iteration
Also, included Driver and Monitor Files
class uart_driver extends uvm_driver#(uart_xtn);
`uvm_component_utils(uart_driver)
wb_agt_config cfg;
virtual wb_if.WB_DRIV vif;
extern function new(string name="uart_driver",uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
extern task drive_item(uart_xtn xtn);
endclass
function uart_driver::new(string name="uart_driver",uvm_component parent);
super.new(name,parent);
endfunction
function void uart_driver::build_phase(uvm_phase phase);
if(!uvm_config_db#(wb_agt_config)::get(this,"","wb_agt_config",cfg))
`uvm_fatal("AGT_CONFIG","Cannot get() env_cfg from config database. Have you set() it")
super.build_phase(phase);
endfunction
function void uart_driver::connect_phase(uvm_phase phase);
vif=cfg.vif;
endfunction
task uart_driver::run_phase(uvm_phase phase);
vif.wb_driv.wb_rst_i<=1;
repeat(2) @(vif.wb_driv);
vif.wb_driv.wb_rst_i<=0;
forever
begin
seq_item_port.get_next_item(req);
drive_item(req);
seq_item_port.item_done();
end
endtask
task uart_driver::drive_item(uart_xtn xtn);
@(vif.wb_driv);
vif.wb_driv.wb_dat_i<=xtn.wb_dat_i;
vif.wb_driv.wb_addr_i<=xtn.wb_addr_i;
vif.wb_driv.wb_we_i<=xtn.wb_we_i;
xtn.wb_stb_i<=1'b1;
xtn.wb_cyc_i<=1'b1;
xtn.wb_sel_i<=4'b0001;
@(vif.wb_driv);
wait(xtn.wb_ack_o);
xtn.wb_cyc_i<=1'b0;
xtn.wb_stb_i<=1'b0;
if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 0)
begin
wait(vif.wb_driv.wb_int_o)
@(vif.wb_driv);
xtn.wb_dat_o <= vif.wb_driv.wb_dat_o;
seq_item_port.put_response(xtn);
end
endtask
Monitor_file
class uart_monitor extends uvm_monitor;
`uvm_component_utils(uart_monitor)
virtual wb_if.WB_MON vif;
wb_agt_config agt_cfg;
uart_xtn xtn;
uvm_analysis_port#(uart_xtn) monitor_port;
function new(string name="uart_monitor",uvm_component parent);
super.new(name,parent);
monitor_port=new("monitor_port",this);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(wb_agt_config)::get(this,"","wb_agt_config",agt_cfg))
`uvm_fatal("AGT_CONFIG","Cannot get() agt_cfg from config database. Have you set() it?")
endfunction
function void connect_phase(uvm_phase phase);
vif=agt_cfg.vif;
endfunction
task run_phase(uvm_phase phase);
forever
collect_data();
endtask
task collect_data();
xtn=uart_xtn::type_id::create("xtn");
wait(vif.wb_mon.wb_ack_o);
@(vif.wb_mon);
xtn.wb_addr_i <= vif.wb_mon.wb_addr_i;
xtn.wb_we_i <= vif.wb_mon.wb_we_i;
if(xtn.wb_addr_i == 3 && xtn.wb_we_i == 1)
xtn.lcr <= vif.wb_mon.wb_dat_i;
if(xtn.wb_addr_i == 1 && xtn.wb_we_i == 1 && xtn.lcr[7] ==1)
xtn.dlr_1 <= vif.wb_mon.wb_dat_i;
if(xtn.wb_addr_i == 0 && xtn.wb_we_i ==1 && xtn.lcr[7]==1)
xtn.dlr_2 <= vif.wb_mon.wb_dat_i;
if(xtn.wb_addr_i == 0 && xtn.wb_we_i == 0 && xtn.lcr[7] == 0)
xtn.rb.push_back(vif.wb_mon.wb_dat_i);
if(xtn.wb_addr_i == 0 && xtn.wb_we_i == 1 && xtn.lcr[7] == 0)
xtn.thr.push_back(vif.wb_mon.wb_dat_i);
if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 1)
xtn.fcr <= vif.wb_mon.wb_dat_i;
if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 0)
begin
wait(vif.wb_mon.wb_int_o)
xtn.iir <= vif.wb_mon.wb_dat_o;
end
endtask
endclass