In reply to Vignesh_18:
Attached here all the files
Transaction file
class uart_xtn extends uvm_sequence_item;
`uvm_object_utils(uart_xtn)
rand logic [2:0] wb_addr_i;
rand logic [7:0] wb_dat_i;
rand logic wb_we_i;
bit wb_stb_i;
bit wb_cyc_i;
bit wb_ack_o;
bit [3:0]wb_sel_i;
bit [7:0]wb_dat_o;
//REGISTERS LIST
bit [7:0] thr[$];
bit [7:0] rb[$];
bit [7:0] ier;
bit [7:0] iir;
bit [7:0] fcr;
bit [7:0] lcr;
bit [7:0] lsr;
bit [7:0] dlr_1;
bit [7:0] dlr_2;
extern function new(string name="uart_xtn");
extern function void do_print(uvm_printer printer);
endclass
function uart_xtn::new(string name="uart_xtn");
super.new(name);
endfunction
function void uart_xtn::do_print(uvm_printer printer);
super.do_print(printer);
printer.print_field("Wishbone Addr", this.wb_addr_i,3,UVM_DEC);
printer.print_field("Wishbone Data",this.wb_dat_i,8,UVM_BIN);
printer.print_field("Wishbone Write",this.wb_we_i,1,UVM_DEC);
//REGISTER PRINTING//
foreach(thr[i])
printer.print_field($sformatf("THR[%0d]",i),this.thr[i],8,UVM_BIN);
foreach(rb[i])
printer.print_field($sformatf("RB[%0d]",i),this.rb[i],8,UVM_BIN);
printer.print_field("IER",this.ier,8,UVM_BIN);
printer.print_field("IIR",this.iir,8,UVM_BIN);
printer.print_field("FCR",this.fcr,8,UVM_BIN);
printer.print_field("LCR",this.lcr,8,UVM_BIN);
printer.print_field("LSR",this.lsr,8,UVM_BIN);
printer.print_field("DLR_1",this.dlr_1,8,UVM_BIN);
printer.print_field("DLR_2",this.dlr_2,8,UVM_BIN);
endfunction
[b]Driver File[/b]
[systemverilog]class uart_driver extends uvm_driver#(uart_xtn);
`uvm_component_utils(uart_driver)
wb_agt_config cfg;
virtual wb_if.WB_DRIV vif;
extern function new(string name="uart_driver",uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function void connect_phase(uvm_phase phase);
extern task run_phase(uvm_phase phase);
extern task drive_item(uart_xtn xtn);
endclass
function uart_driver::new(string name="uart_driver",uvm_component parent);
super.new(name,parent);
endfunction
function void uart_driver::build_phase(uvm_phase phase);
if(!uvm_config_db#(wb_agt_config)::get(this,"","wb_agt_config",cfg))
`uvm_fatal("AGT_CONFIG","Cannot get() env_cfg from config database. Have you set() it")
super.build_phase(phase);
endfunction
function void uart_driver::connect_phase(uvm_phase phase);
vif=cfg.vif;
endfunction
task uart_driver::run_phase(uvm_phase phase);
vif.wb_driv.wb_rst_i<=1;
repeat(2) @(vif.wb_driv);
vif.wb_driv.wb_rst_i<=0;
forever
begin
seq_item_port.get_next_item(req);
drive_item(req);
seq_item_port.item_done();
end
endtask
task uart_driver::drive_item(uart_xtn xtn);
`uvm_info(get_type_name(),"before clk event",UVM_MEDIUM)
@(vif.wb_driv);
`uvm_info(get_type_name(),"after clk event",UVM_MEDIUM)
vif.wb_driv.wb_dat_i<=xtn.wb_dat_i;
vif.wb_driv.wb_addr_i<=xtn.wb_addr_i;
vif.wb_driv.wb_we_i<=xtn.wb_we_i;
`uvm_info(get_type_name(),"before clk event",UVM_MEDIUM)
@(vif.wb_driv);
`uvm_info(get_type_name(),"after clk event",UVM_MEDIUM)
xtn.wb_stb_i<=1'b1;
xtn.wb_cyc_i<=1'b1;
xtn.wb_sel_i<=4'b0001;
//@(vif.wb_driv);
`uvm_info("Debug","waiting for ack",UVM_LOW)
wait(xtn.wb_ack_o);
`uvm_info(get_type_name(),"before clk event",UVM_MEDIUM)
@(vif.wb_driv);
`uvm_info(get_type_name(),"after clk event",UVM_MEDIUM)
xtn.wb_cyc_i<=1'b0;
xtn.wb_stb_i<=1'b0;
if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 0)
begin
`uvm_info("Debug","waiting for int_o signal",UVM_LOW)
wait(vif.wb_driv.wb_int_o)
`uvm_info(get_type_name(),"Before clk event",UVM_MEDIUM)
@(vif.wb_driv);
`uvm_info(get_type_name(),"after clk event",UVM_MEDIUM)
xtn.wb_dat_o <= vif.wb_driv.wb_dat_o;
seq_item_port.put_response(xtn);
end
endtaskMonitor File
class uart_monitor extends uvm_monitor;
`uvm_component_utils(uart_monitor)
virtual wb_if.WB_MON vif;
wb_agt_config agt_cfg;
uart_xtn xtn;
uvm_analysis_port#(uart_xtn) monitor_port;
function new(string name="uart_monitor",uvm_component parent);
super.new(name,parent);
monitor_port=new("monitor_port",this);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
if(!uvm_config_db#(wb_agt_config)::get(this,"","wb_agt_config",agt_cfg))
`uvm_fatal("AGT_CONFIG","Cannot get() agt_cfg from config database. Have you set() it?")
endfunction
function void connect_phase(uvm_phase phase);
vif=agt_cfg.vif;
endfunction
task run_phase(uvm_phase phase);
forever
collect_data();
endtask
task collect_data();
task collect_data();
xtn=uart_xtn::type_id::create("xtn");
`uvm_info("Debug","Waiting for ack",UVM_LOW);
wait(vif.wb_mon.wb_ack_o);
`uvm_info(get_type_name(),"Before clk event",UVM_MEDIUM)
@(vif.wb_mon);
`uvm_info(get_type_name(),"After clk event",UVM_MEDIUM)
xtn.wb_addr_i <= vif.wb_mon.wb_addr_i;
xtn.wb_we_i <= vif.wb_mon.wb_we_i;
if(xtn.wb_addr_i == 3 && xtn.wb_we_i == 1)
xtn.lcr <= vif.wb_mon.wb_dat_i;
if(xtn.wb_addr_i == 1 && xtn.wb_we_i == 1 && xtn.lcr[7] ==1)
xtn.dlr_1 <= vif.wb_mon.wb_dat_i;
if(xtn.wb_addr_i == 0 && xtn.wb_we_i ==1 && xtn.lcr[7]==1)
xtn.dlr_2 <= vif.wb_mon.wb_dat_i;
if(xtn.wb_addr_i == 0 && xtn.wb_we_i == 0 && xtn.lcr[7] == 0)
xtn.rb.push_back(vif.wb_mon.wb_dat_i);
if(xtn.wb_addr_i == 0 && xtn.wb_we_i == 1 && xtn.lcr[7] == 0)
xtn.thr.push_back(vif.wb_mon.wb_dat_i);
if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 1)
xtn.fcr <= vif.wb_mon.wb_dat_i;
if(xtn.wb_addr_i == 2 && xtn.wb_we_i == 0)
begin
wait(vif.wb_mon.wb_int_o)
xtn.iir <= vif.wb_mon.wb_dat_o;
end
endtask
endclassSeqeunce File
class base_seq extends uvm_sequence#(uart_xtn);
`uvm_object_utils(base_seq)
function new(string name="base_seq");
super.new(name);
endfunction
endclass
class seq1 extends base_seq;
`uvm_object_utils(seq1);
function new(string name="seq1");
super.new(name);
endfunction
virtual task body();
begin
req=uart_xtn::type_id::create("req");
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b1000_0000;wb_we_i==1'b1;wb_addr_i==3;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0000_0000;wb_we_i==1'b1;wb_addr_i==1;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0011_0110;wb_we_i==1'b1;wb_addr_i==0;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0000_0011;wb_we_i==1'b1;wb_addr_i==3;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0000_0001;wb_we_i==1'b1;wb_addr_i==1;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0000_0110;wb_we_i==1'b1;wb_addr_i==2;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0000_0111;wb_we_i==1'b1;wb_addr_i==0;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_addr_i==2; wb_we_i==0;})
finish_item(req);
get_response(req);
if(req.wb_dat_o == 8'b0000_0110)
begin
start_item(req);
assert(req.randomize() with {wb_we_i==0;wb_addr_i==5;})
finish_item(req);
end
if(req.wb_dat_o == 8'b0000_0100)
begin
start_item(req);
assert(req.randomize() with { wb_we_i == 0 ;wb_addr_i == 0 ;})
finish_item(req);
end
if(req.wb_dat_o == 8'b0000_1100)
begin
start_item(req);
assert(req.randomize() with {wb_we_i == 0;wb_addr_i == 0;})
finish_item(req);
end
if(req.wb_dat_o == 8'b0000_0010)
begin
start_item(req);
assert(req.randomize() with { wb_we_i == 1;wb_addr_i == 0;wb_dat_i == 8'b0000_0111;})
finish_item(req);
end
end
endtask
endclass
class seq2 extends base_seq;
`uvm_object_utils(seq2)
function new(string name="seq2");
super.new(name);
endfunction
virtual task body();
begin
req=uart_xtn::type_id::create("req");
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b1000_0000;wb_we_i==1'b1;wb_addr_i==3;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0000_0000;wb_we_i==1'b1;wb_addr_i==1;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0001_1011;wb_we_i==1'b1;wb_addr_i==0;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0000_0011;wb_we_i==1'b1;wb_addr_i==3;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0000_0001;wb_we_i==1'b1;wb_addr_i==1;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0000_0110;wb_we_i==1'b1;wb_addr_i==2;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_dat_i==8'b0000_0111;wb_we_i==1'b1;wb_addr_i==0;})
finish_item(req);
start_item(req);
assert(req.randomize() with {wb_addr_i==2; wb_we_i==0;})
finish_item(req);
get_response(req);
if(req.wb_dat_o == 8'b0000_0110)
begin
start_item(req);
assert(req.randomize() with {wb_we_i==0;
wb_addr_i==5;})
finish_item(req);
end
if(req.wb_dat_o == 8'b0000_0100)
begin
start_item(req);
assert(req.randomize() with { wb_we_i ==0 ;
wb_addr_i ==0 ;})
finish_item(req);
end
if(req.wb_dat_o == 8'b0000_1100)
begin
start_item(req);
assert(req.randomize() with {wb_we_i == 0;
wb_addr_i == 0;})
finish_item(req);
end
if(req.wb_dat_o == 8'b0000_0010)
begin
start_item(req);
assert(req.randomize() with {wb_we_i == 1;
wb_addr_i == 0;
wb_dat_i == 8'b0000_0111;})
finish_item(req);
end
end
endtask
endclass
TEST FILE
class uart_base_test extends uvm_test;
`uvm_component_utils(uart_base_test)
uart_env envh;
uart_env_config env_config;
wb_agt_config agt_config[];
int no_of_duts = 2;
int no_of_agts = 2;
int has_wb_agent=1;
// int has_virtual_inf=2;
extern function new(string name="uart_base_test",uvm_component parent);
extern function void build_phase(uvm_phase phase);
extern function void config_uart();
// extern function void end_of_elaboration_phase(uvm_phase phase);
endclass
function uart_base_test::new(string name="uart_base_test",uvm_component parent);
super.new(name,parent);
endfunction
function void uart_base_test::config_uart();
if(has_wb_agent)
begin
agt_config=new[no_of_duts];
foreach(agt_config[i])
begin
agt_config[i]=wb_agt_config::type_id::create($sformatf("agt_config[%0d]",i));
if(!uvm_config_db#(virtual wb_if)::get(this," ",$sformatf("vif_%0d",i),agt_config[i].vif))
`uvm_fatal("VIF_CONFIG","Cannot get() interface vif from uvm_config_db. Have you set() it?")
agt_config[i].is_active = UVM_ACTIVE;
env_config.agt_config[i]=agt_config[i];
end
end
env_config.no_of_agts=no_of_agts;
env_config.no_of_duts=no_of_duts;
env_config.has_wb_agent= has_wb_agent;
endfunction
function void uart_base_test::build_phase(uvm_phase phase);
env_config=uart_env_config::type_id::create("env_config");
if(has_wb_agent)
env_config.agt_config=new[no_of_duts];
config_uart;
uvm_config_db#(uart_env_config)::set(this,"*","uart_env_config",env_config);
super.build_phase(phase);
//ENVIRONMENT CREATION//
envh=uart_env::type_id::create("envh",this);
endfunction
/*function void uart_base_test::end_of_elaboration_phase(uvm_phase phase);
uvm_top.print_topology();
endfunction*/
class TC1 extends uart_base_test;
`uvm_component_utils(TC1)
v_seq1 vs1;
function new(string name="TC1",uvm_component parent);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction
task run_phase(uvm_phase phase);
phase.raise_objection(this);
vs1=v_seq1::type_id::create("vs1");
vs1.start(envh.vsqrh);
phase.drop_objection(this);
endtask
endclass
