In my experience it’s risky to use assert() to wrap code that should always be executed since sometimes people will disable assertions using $assertoff. The latest version of the UVM cookbook shows it both ways in different places, using asserts and ifs.
This example shows one spot where assert is used, from
Sequences/Generation | Verification Academy Exploiting > The Sequence As An Object > Randomized Fields
assert(seq.randomize() with {src_addr == 32'h0100_0800;
dst_addr inside {[32'h0101_0000:32'h0103_0000]};
transfer_size == 128;});
If you don’t want to use assert or if, then directly drive the values with sequence handle as shown below:
start_item(seq);
seq.src_addr=32’d0100_0100;
transfer_size=128;
finish_item(seq);
In reply to kireeti1192:
This is valid only for non-randomized data. The randomize method returns in any way a value.
What you can do is
if(!seq.randomize() with {src_addr == 32'h0100_0800;
dst_addr inside {[32'h0101_0000:32'h0103_0000]};
transfer_size == 128;})
`uvm_error(get_type_name(), "Randomization failed")
In reply to chr_sue:
I believe the original question is about the choice between using if or assert statements to check the result of calling randomize().
Actually, my problem with the original code is it does not call umm_error or umm_fatal on failure. The UVM methodology requires all errors be trapped by a UVM_ERROR or greater severity. This is needed for managing regressions properly and for catching expected errors with negative tests.
Many people ignore the warnings they get when calling randomize() without checking the result (Some tools do not even generate a warning). So their test improperly carries on, leaving their random variables unmodified.
Using an immediate assertion was a quick and easy way of generating an error. It was unfortunate that SystemVerilog later added the $assertoff functionality to immediate assertions and had it not evaluate the condition. It should have just turned off the checking.
But now that the UVM requires calling `umm_error when failing, it’s a few characters less typing to use the if statement and you get the same functionality as the assert without the risk of having it turned off,
In reply to dave_59:
Looks like the UVM cookbook coding standards have a rule that assert() should not be used.
4.3 Rule: Use if rather than assert to check the status of method calls
Assert results in the code check appearing in the coverage database, which is undesired. Incorrectly turning off the action blocks of assertions may also produce undesired results.
– SystemVerilog Guidelines | UVM Cookbook
I’d recommend that the code examples in the UVM Cookbook be updated to follow the rules of the cookbook so people don’t get bad habits from the Cookbook