Should I have to declare the reg_model to the tb and env?

Dear All,

I’m confused that the declaration of reg_model implementation.
and I want to know what is the difference if I don’t implement reg_model at env hierarchy.

For example,

uart_ctrl_tb.sv


class uart_ctrl_tb extends uvm_env

uart_ctrl_env uart_ctrl0
// declare register model
uart_ctrl_reg_model_c reg_model //<-------Here reg_model declared
...
endclass

uart_ctrl_env.sv


class uart_ctrl_env extends uvm_env

uart_ctrl_reg_model_c reg model; //<-------Here reg_model declared also too.

`uvm_component_utils_begin(uart_strl_env)
  `uvm_field_object(reg_model, UVM_DEFAULT);
...
`uvm_component_utils_end
...
endclass

From here, If I do comment out the reg_model as the below,
Is it possible way? I mean the former way is twice declared the reg_model.
It seems that redundant so I want to comment the reg_model.
Is there any special reason the reason is declared at the both side tb and env?

uart_ctrl_env.sv


class uart_ctrl_env extends uvm_env
//uart_ctrl_reg_model_c reg model;

`uvm_component_utils_begin(uart_strl_env)
//  `uvm_field_object(reg_model, UVM_DEFAULT);
...
`uvm_component_utils_end
...
endclass

In reply to UVM_LOVE:

Firstly I try to understand why do you have a hierarchy of env’s: uart_ctrl_tb and uart_ctrl_env.
You may declare in both env’s handles to your register model.
But this night depend on your coding guidelines in your company. Anyway having handles to the reg_model in both envs does not add overhead to your testbench.