Sharing values between 2 sequences

UVM
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1

Hi,

Here is my question. I am trying to verify 2 port RAM.
I have one rd_agent hooked to one of the interface and wr_agent hooked to other interface. so read_sequence should only issue a read to a address to which write_agent has already initialized the value.

I need some communication mechanism between 2 sequence. How do I achieve this?

2

In reply to tex_mex:

I usually use uvm_event_pool to communicate between components or sequences. uvm_event_pool also let you pass a data value from a sequence to another. Simple idea:

  1. read_sequence waits for a event (uvm_event) to be triggered using wait_trigger_data(address) task before it issues a read to address which is received from wait_trigger_data task.

  2. write_sequence initializes a value to address, then trigger and send address value to read_sequence using trigger(address) function.

Code example: http://verificationsharing.blogspot.sg/2018/03/uvm-case-study-uvm-event.html

3

In reply to tex_mex:

Ideally you would use a virtual sequence. The purpose of a virtual sequence is to co-ordinate the execution of sub-sequences, which includes sharing required data between them, such as addresses.

You should never use event pools as these introduce unnecessary complexity and reduces the re-usability of these sequences.

4

In reply to cgales:

Yes, you are right. Using virtual sequence is the best way to manage sub sequences.