Shared address maps in uvm_reg_block

UVM
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1

I have a top level uvm_reg_block with 2 maps, A and B. I add a subblock of type uvm_reg_block named C to both using add_submap(see below)

this.A= create_map(“A”, UVM_REG_ADDR_WIDTH'h0, 4, UVM_LITTLE_ENDIAN, 1); this.B= create_map("B", UVM_REG_ADDR_WIDTH’h0, 4, UVM_LITTLE_ENDIAN, 1);
this.A.add_submap(this.C.default_map,UVM_REG_ADDR_WIDTH'h0); this.B.add_submap(this.C.default_map,UVM_REG_ADDR_WIDTH’h0);

I see the following error reported:
UVM_ERROR : reporter [RegModel] Map ‘m_reg.C.default_map’ is already a child of map ‘m_reg.A’. Cannot also be a child of map ‘m_reg.B’

Is there a way to get around this issue? Does UVM not support having the same uvm_reg_block in multiple maps?

I tried to create multiple instances of subblock C namely C_A and C_B:

this.A.add_submap(this.C_A.default_map,UVM_REG_ADDR_WIDTH'h0); this.B.add_submap(this.C_B.default_map,UVM_REG_ADDR_WIDTH’h0);

The issue with the above code is - when a register is accessed in C_A reg block, the ral mirror is updated only for C_A and hence C_B’s ral mirror is outdated even if both the reg blocks C_A and C_B point to same registers in the design.

Thanks!

2

In reply to ash7:

I just ran into the same issue. The documentation says you can do this if certain conditions are met:
*
An address map may be added to multiple address maps if it is accessible from multiple physical interfaces. An address map may only be added to an address map in the grand-parent block of the address submap.
*
It’s not totally clear to me what that part about the grand-parent block is trying to say. I do have two physical interfaces.

Anyway, if you look at the add_submap function in src/reg/uvm_reg_map.svh, it prints the error you describe if parent_map != null.
This is true in UVM-1.1d and 1.2 as well. The comment on that section says “Can not have more than one parent (currently)”. So, the answer is it can’t be done, period. Until some time in the future, when maybe the code will match the documentation?!?!