Hello,
i am quite new to UVM topic and System Verilog. I am trying to work around this existing example on eda playground to add an internal signal in the design module adder, example:
reg[3:0] d;
and access this on the environment.sv level or test.sv to set it to some value say 6 and print it out as-well.
I tried to bind the internal signal on top level, but it seems to not work.
bind DUT.adder intf i_intf(d);
what are the ways to achieve this or say best practice?
can anyone please guide me in this ?
thanks a lot in advance
“seems not to work” needs a better explanation. This is not a UVM testbench, yet you have an extraneous uvm_config_db reference causing a compiler error.
You have two interface instances; one in your tbench_top module, and one that you are trying to bind.
You need to build a uvm testbench for your uvm_config_db set to work / make sense.
You did mention that you are new to System Verilog / UVM. You will need to do a lot more reading on UVM basics before you can get the piece of code you have to work.
If you are not interested in going the UVM route, and rather just stick to System-Verilog, you should just drop the uvm_config_db set and continue using just SV.
Thank you for your reply. Is there any websites or tutorials for building simpler UVM testbenches with step by step details? I did check this ‘Hello World’ program (A simple “Hello, World!” in UVM – UVM Padawan), but perhaps some more examples to understand will be great.
Even better approach would be to take a look at the many resources that this very site provides. Coding guidelines, downloadable examples, and video courses.