Setting endianness for every uvm_reg

UVM
,
1

Hi,
Assume I can’t change reg2bus of adapter, and I want to write in register in different endianness, how can I do ?
I have already try
this.default_map = create_map(“”, 0, 4, UVM_LITTLE_ENDIAN,0), change on the fourth argument (UVM_LITTLE_FIFO …)
But they all don’t work

2

In reply to Edison_yu:

class jelly_bean_taste_reg extends uvm_reg;
   `uvm_object_utils( jelly_bean_taste_reg )
 
   rand uvm_reg_field taste;
 
   function new( string name = "jelly_bean_taste_reg" );
      super.new( .name( name ), .n_bits( 2 ), .has_coverage( UVM_NO_COVERAGE ) );
   endfunction: new
 
   virtual function void build();
      taste = uvm_reg_field::type_id::create("taste");
      taste.configure( .parent                 ( this ),
                       .size                   ( 2    ),
                       .lsb_pos                ( 0    ),
                       .access                 ( "RO" ),
                       .volatile               ( 1    ),
                       .reset                  ( 0    ),
                       .has_reset              ( 1    ),
                       .is_rand                ( 1    ),
                       .individually_accessible( 1    ) );
   endfunction: build
endclass: jelly_bean_taste_reg

If you want to change the endianness while writing into the register then you need to change the lsb_pos like above mention code. Suppose your register size is 8 and you want to write as bigendian then you can give .lsb_pos as 7. Then your 7th position bit will be written in register’s 0th location.

3

In reply to Subhra Bera:
thanks , got it
so what does the endianness meaning in create_map() ?
It doesn’t mean the RAL mapping way?