Set function is not updating desired value of uvm_reg_field with access "W1T"

UVM
,
1

I have a 32 register with 3 fields.
Field a → Bit [1:0] → “RW”
Field b → Bit [5:2] → “W1T”
Field c → Bit [31:6] → “RO”

The initial value of register is 32’h0 and I am setting the desired value with 32’h8741_256a.
The expected value with get function is 32’h0000_002a but I am receiving 32’h0000_0002.

2

In reply to kishore_tavva:

The access type W1T does not belong to the default access types. You have to enable it explicitly.

3

In reply to chr_sue:

Hi Chr_sue,
In the register definition, for field ‘b’, I have explicitly defined the access as “W1T”.

4

In reply to kishore_tavva:

I understand, but not all possible access types are supported automatically by the RAL layer. You have to enable some of these specific types.

5

In reply to chr_sue:

Hi Chr_sue,
Could you please help me on how to enable “W1T” access for field ‘b’.

6

In reply to kishore_tavva:

You have to call ‘set_access(string mode)’ on the specific reg_field where mode is your access mode like this
your_reg_field.aet_access(“W1T”);