Hi All,
I am trying to set the constraint and not sure how to achieve the desired result.
//code start
typedef enum bit [7:0] {instr1, instr2, instr3, instr4, instr5} e_instr; // I have an enum with set of valid instructions in it.
typedef enum (40, 80, 104) e_FreqFlag;
class my_seq_item extends uvm_seq_item;
rand e_instr inst;
e_FreqFlag Fflag;
byte opcode;
bit [1:0] mode;
int AddrCycle;
int DummyCycle;
constraint c_inst { inst=instr1 -> {opcode=8'h00; mode=2'b00; AddrCycle=0; DataCycle=0; Fflag=0;}
inst=instr2 -> {opcode=8'h00; mode=2'b01; AddrCycle=0; DataCycle=0; Fflag=0;} // Note here its instr2 same as the one below
inst=instr2 -> {opcode=8'h00; mode=2'b10; AddrCycle=1; DataCycle=0; Fflag=0;} // note the field mode & AddrCycle has chaged.
#inst=instr2 -> {opcode=8'h00; mode inside {2'b01,2'10}; if(mode=01)AddrCycle=0 else AddrCycle=1; DataCycle=0; Fflag=0;}
// Pseudo code for what i wish to achieve is in above line commented.. is there something nested constaint i can use to achive this.
}
endclass
//code end
Thanks for your help and guidance.