Sequencer m_req_fifo depth

UVM
, ,
1

class ahb_slave_write_wait_seq extends ahb_slave_sequence_base;

//uvm factory registery
`uvm_object_utils(ahb_slave_write_wait_seq)

//semaphore for multi-thread
semaphore phase_lock = new(1);

//uvm standard method: new
function new(string name = "ahb_slave_write_wait_seq");
    super.new(name);
endfunction

//user define method: beat_transfer
virtual task beat_transfer();
    ahb_slave_item req;
    ahb_slave_item rsp;
    req = new();
    rsp = new();

    forever begin
        phase_lock.get();       //get the key

        `uvm_info(get_name(), $sformatf("slave start_item"), UVM_HIGH);
        //get request
        start_item(req);
        assert(req.randomize() with{req.hresp == 2'b00;});
        `uvm_info(get_name(), $sformatf("req.hready_low_cycle is %0d", req.hready_low_cycle), UVM_HIGH);
        finish_item(req);
        `uvm_info(get_name(), $sformatf("slave finish_item"), UVM_HIGH);

        phase_lock.put();       //put back the key

        //put response
        start_item(rsp);
        rsp.my_copy(req);
        if(rsp.hresp == 2'b00) begin                //when slave agent response is OKAY, load wdata to memory
            if(rsp.cmd) begin
                memory[req.addr] = req.wdata;
            end
            else begin
                if(!memory.exists(rsp.addr)) begin
                    memory[rsp.addr] = 32'heeeeffff;
                end
                assert(rsp.randomize() with {rsp.rdata == memory[rsp.addr];});
                `uvm_info(get_name(), $sformatf("rsp.hready_low_cycle is %0d", rsp.hready_low_cycle), UVM_HIGH);
            end
        end
        finish_item(rsp);
    end
endtask

//uvm standard method: body
virtual task body();
    //multi-thread
    fork
        beat_transfer();
        beat_transfer();
    join
endtask;

endclass

//:ts=4,sw=4

During simulation,i got a log below:
uvm_fatal:Sequencer send_request not able to put to fifo, depth 1

I don’t know why m_req_fifo.size() = 1, can someone help me?
Thankyou!

2

The expectation is that sequencer gives only one item to driver and waits for the response from driver (if any).
If you intend to model pipelined access, please refer to uvm cookbook from verification academy which provides examples of pipelined driver and sequence.